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    DATA PROCESSING SYSTEMS
    1.
    发明申请
    DATA PROCESSING SYSTEMS 有权

    公开(公告)号：US20250038991A1

    公开(公告)日：2025-01-30

    申请号：US18361261

    申请日：2023-07-28

    Applicant: Arm Limited

    Inventor： Vladimir Dolzhenko ,  Håkan Lars-Göran Persson

    IPC: H04L9/32 ,  H04N19/124 ,  H04N19/172

    Abstract: A data processing system that comprises an encoder, and a communication system is disclosed. Compressed data produced by the encoder is decompressed to produce first decompressed data, and a first signature representative of the first decompressed data is generated. Compressed data that has been transferred by the communication system is decompressed to produce second decompressed data, and a second signature representative of the second decompressed data is generated. The first signature and the second signature are compared, and the comparison is used to determine whether an error has occurred.

    Invalidation of entries in address translation storage
    2.
    发明授权
    Invalidation of entries in address translation storage 有权

    公开(公告)号：US10747681B1

    公开(公告)日：2020-08-18

    申请号：US16356016

    申请日：2019-03-18

    Applicant: Arm Limited

    Inventor： Håkan Lars-Göran Persson

    IPC: G06F12/10 ,  G06F12/1018 ,  G06F12/0891 ,  G06F12/1045 ,  G06F12/0808

    Abstract: Apparatuses and methods for address translation invalidation are provided. In an apparatus having address translation storage which stores merged address translation information for multiple address translation stages, a set of counters are provided to hold a set of counter values. Entries in the address translation storage are stored with identifiers of first and second counters selected from the set of counters in dependence on respective context information for a first stage and a second stage of address translation together with a counter value of each counter. In response to an invalidation request specifying a first or second addressing scheme invalidation context a counter of the set of counters is selected in dependence on the first or second addressing scheme invalidation context and its value is modified. Subsequently an entry in the address translation storage is determined to be invalid when either the first counter value does not match a current value of the first counter or the second counter value does not match a current value of the second counter.

    Efficient evict for cache block memory
    3.
    发明授权
    Efficient evict for cache block memory 有权

    公开(公告)号：US11954038B2

    公开(公告)日：2024-04-09

    申请号：US17305991

    申请日：2021-07-19

    Applicant: Arm Limited

    Inventor： Olof Henrik Uhrenholt ,  Håkan Lars-Göran Persson ,  Jakob Axel Fries

    IPC: G06F12/0888 ,  G06T1/20 ,  G06T1/60 ,  G06T9/00

    CPC classification number: G06F12/0888 ,  G06T1/20 ,  G06T1/60 ,  G06T9/00 ,  G06F2212/1044

    Abstract: A data processing system includes a memory system, a processor and a cache system. The cache system includes a cache and a data encoder associated with the cache. The data encoder encodes blocks of uncompressed data having a particular data size for storing in the memory system. The processor is configured, when an array of data has a data size equal to the particular data size or is able to be combined with one or more other arrays of data already written to the cache to provide a plurality of arrays of data having a data size that is equal to the particular data size, to output the array of data from the processor to the data encoder, bypassing the cache, for encoding as or as part of a block of data having the particular data size.

    DATA PROCESSING SYSTEMS
    4.
    发明申请
    DATA PROCESSING SYSTEMS 审中-公开
    数据处理系统

    公开(公告)号：US20170060637A1

    公开(公告)日：2017-03-02

    申请号：US15246949

    申请日：2016-08-25

    Applicant: ARM Limited

    Inventor： Håkan Lars-Göran Persson ,  Steven John Price ,  Thomas James Cooksey

    IPC: G06F9/50 ,  G06T1/20 ,  G06F9/46

    Abstract: A data processing system includes a host processor that executes an operating system and an accelerator operable to process data under the control of the operating system executing on the host processor. The accelerator can be switched between a normal mode of operation and a protected mode of operation in which the side channel information that can be provided by the accelerator to the host processor is restricted. The data processing system also includes a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

    Abstract translation: 数据处理系统包括执行操作系统的主处理器和可操作以在主处理器上执行的操作系统的控制下处理数据的加速器。 加速器可以在正常操作模式和保护操作模式之间切换，其中加速器可以向主机处理器提供的侧信道信息被限制。 数据处理系统还包括用于将加速器从其正常操作模式切换到保护操作模式以及从保护操作模式到正常操作模式的机制。

    Enforcing data protection in an interconnect
    7.
    发明授权
    Enforcing data protection in an interconnect 有权

    公开(公告)号：US10078589B2

    公开(公告)日：2018-09-18

    申请号：US14700259

    申请日：2015-04-30

    Applicant: ARM LIMITED

    Inventor： Daniel Sara ,  Antony John Harris ,  Håkan Lars-Göran Persson ,  Andrew Christopher Rose ,  Ian Bratt

    IPC: G06F12/08 ,  G06F12/14 ,  G06F12/0831

    CPC classification number: G06F12/0831 ,  G06F12/0833 ,  G06F12/1491 ,  G06F2212/1052

    Abstract: Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.

    Task dispatch
    8.
    发明授权
    Task dispatch 有权

    公开(公告)号：US11550620B2

    公开(公告)日：2023-01-10

    申请号：US17190729

    申请日：2021-03-03

    Applicant: Arm Limited

    Inventor： Håkan Lars-Göran Persson ,  Frederic Claude Marie Piry ,  Matthew Lucien Evans ,  Albin Pierrick Tonnerre

    IPC: G06F9/48 ,  G06F12/10 ,  G06F9/30 ,  G06F9/38

    Abstract: Apparatuses and methods are disclosed for performing data processing operations in main processing circuitry and delegating certain tasks to auxiliary processing circuitry. User-specified instructions executed by the main processing circuitry comprise a task dispatch specification specifying an indication of the auxiliary processing circuitry and multiple data words defining a delegated task comprising at least one virtual address indicator. In response to the task dispatch specification the main processing circuitry performs virtual-to-physical address translation with respect to the at least one virtual address indicator to derive at least one physical address indicator, and issues a task dispatch memory write transaction to the auxiliary processing circuitry comprises the indication of the auxiliary processing circuitry and the multiple data words, wherein the at least one virtual address indicator in the multiple data words is substituted by the at least one physical address indicator.

    DATA PROCESSING SYSTEMS
    9.
    发明申请
    DATA PROCESSING SYSTEMS 有权

    公开(公告)号：US20220027281A1

    公开(公告)日：2022-01-27

    申请号：US17305991

    申请日：2021-07-19

    Applicant: Arm Limited

    Inventor： Olof Henrik Uhrenholt ,  Håkan Lars-Göran Persson ,  Jakob Axel Fries

    IPC: G06F12/0888 ,  G06T1/60 ,  G06T9/00 ,  G06T1/20

    Abstract: A data processing system includes a memory system, a processor and a cache system. The cache system includes a cache and a data encoder associated with the cache. The data encoder encodes blocks of uncompressed data having a particular data size for storing in the memory system. The processor is configured, when an array of data has a data size equal to the particular data size or is able to be combined with one or more other arrays of data already written to the cache to provide a plurality of arrays of data having a data size that is equal to the particular data size, to output the array of data from the processor to the data encoder, bypassing the cache, for encoding as or as part of a block of data having the particular data size.

    Cache memory
    10.
    发明授权
    Cache memory 有权

    公开(公告)号：US10423534B2

    公开(公告)日：2019-09-24

    申请号：US15369193

    申请日：2016-12-05

    Applicant: ARM LIMITED

    Inventor： Håkan Lars-Göran Persson

    IPC: G06F12/0895 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/128 ,  G06F12/12

    Abstract: A cache memory, such as a translation lookaside buffer cache 16, includes a plurality of blocks of bit storage circuits 26 which can operate in either a first mode to store a plurality of shared-tagged data values having a shared tag, which his stored in a tag memory 24, or in a second mode to store a plurality of individual-tag data values and respective individual tags. The tag entries within the tag memory comprise the shared tag value for a given block operating in the first mode and a composite value for a given block operating in the second mode. The composite value includes a discriminator value indicative of the respective individual tags, such as a hash value or a Bloom filter value calculated in dependence upon the individual tags, using which potential matches with the individual tags may be identified from the discriminator value.

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