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公开(公告)号：US09997217B1
公开(公告)日：2018-06-12
申请号：US15477516
申请日：2017-04-03
Applicant: ARM Limited
Inventor： Ankur Goel , Munish Kumar , Nitin Jindal , Rahul Mathur , Shruti Aggarwal , Bikas Maiti , Yew Keong Chong
CPC classification number: G11C7/12 , G11C7/1096 , G11C11/4087 , G11C11/419
Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.
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公开(公告)号：US11017142B1
公开(公告)日：2021-05-25
申请号：US17010630
申请日：2020-09-02
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Shruti Aggarwal , Mohit Chanana , Hsin-Yu Chen , Kyung Woo Kim
IPC: G06F30/343 , G06F30/337 , G06F30/20 , G06F1/28 , G06F119/12 , G06F119/06 , G06F30/3308
Abstract: According to one implementation of the present disclosure, a method includes determining one or more of a read current threshold, a leakage current threshold or a minimum assist voltage threshold; identifying a logic design, wherein the logic design is based the on one or more of the read current threshold, the leakage current threshold, or the minimum assist voltage threshold; identifying a bitcell-type and a corresponding version of the bitcell-type, wherein each version of the bitcell-type is associated with performance and power attributes of a bitcell of a memory array; and determining a memory optimization mode based on the identified logic design and the identified version of the bitcell-type.
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公开(公告)号：US10515684B2
公开(公告)日：2019-12-24
申请号：US15823490
申请日：2017-11-27
Applicant: Arm Limited
Inventor： Mohit Chanana , Ankur Goel , Shruti Aggarwal
IPC: G11C11/413 , G11C11/408 , G11C11/418 , G11C11/419 , G11C8/08
Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.
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公开(公告)号：US20190164590A1
公开(公告)日：2019-05-30
申请号：US15823490
申请日：2017-11-27
Applicant: Arm Limited
Inventor： Mohit Chanana , Ankur Goel , Shruti Aggarwal
IPC: G11C11/408 , G11C11/419 , G11C11/418
CPC classification number: G11C11/4085 , G11C8/08 , G11C11/4087 , G11C11/418 , G11C11/419
Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.
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