公开(公告)号：US08941428B2

公开(公告)日：2015-01-27

申请号：US14248555

申请日：2014-04-09

Applicant: ARM Limited

Inventor： Virgile Javerliac ,  Yannick Marc Nevers ,  Laurent Christian Sibuet ,  Selma Laabidi

IPC: H03K3/289 ,  H03K3/037 ,  G11C11/412 ,  G11C19/28 ,  H03K3/012

CPC classification number: H03K3/037 ,  G11C11/412 ,  G11C19/28 ,  H03K3/012 ,  H03K3/0372

Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.

Abstract translation: 锁存电路具有用于接收数据值的输入，用于输出表示数据值的值的输出，用于接收时钟信号的时钟信号输入; 和通行证。 反馈回路具有并联布置在两个反相器件之间的两个开关电路，两个开关电路中的第一个被配置为截止并且不响应于具有预定控制值的控制信号而导通，并且两个开关电路中的第二个是 被配置为接通并响应于具有预定控制值的控制信号而导通。 控制两个开关电路的控制信号被链接，使得开关装置切换其导通状态，并且访问控制装置一起起作用以更新反馈回路内的数据值。

公开(公告)号：US08885429B1

公开(公告)日：2014-11-11

申请号：US13915918

申请日：2013-06-12

Applicant: ARM Limited

Inventor： Nicolaas Klarinus Johannes Van Winkelhoff ,  Pierre Lemarchand ,  Bastien Jean Claude Aghetti ,  Virgile Javerliac

IPC: G11C7/00 ,  G11C29/52

CPC classification number: G11C29/52 ,  G11C7/20 ,  G11C7/24 ,  G11C11/419 ,  G11C16/14 ,  G11C16/22

Abstract: A memory device including an array of memory cells arranged as a plurality of rows and columns. Write circuitry then controls a voltage level of the associated at least one bit line for each of the addressed memory cells to cause write data to be written into the addressed memory cells. In the presence of an asserted erase signal, a decoder circuitry's operation is modified such that it issues, independently of the clock signal, an asserted word line signal on the word line associated with each row in a predetermined erase region of the array. Further, the write circuitry's operation is modified so that it controls the voltage level of the associated at least one bit line for each memory cell in the predetermined erase region, in order to cause erase write data to be written into the memory cells of the predetermined erase region.

Abstract translation: 一种存储器件，包括布置成多个行和列的存储单元阵列。 然后，写入电路控制每个寻址的存储器单元的相关联的至少一个位线的电压电平，以使写入数据被写入寻址的存储单元。 在有断言的擦除信号的存在下，解码器电路的操作被修改，使得其独立于时钟信号发出在阵列的预定擦除区域中与每行相关联的字线上的断言的字线信号。 此外，修改写入电路的操作，使得其控制预定擦除区域中的每个存储器单元的相关联的至少一个位线的电压电平，以便将擦除写入数据写入到预定的擦除区域的存储器单元中 擦除区域。