公开(公告)号：US10558585B2

公开(公告)日：2020-02-11

申请号：US15355785

申请日：2016-11-18

Applicant: ARM Limited

Inventor： Yannick Marc Nevers ,  Bastien Jean Claude Aghetti ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  Stephane Zonza

IPC: G06F12/14 ,  G06F21/79 ,  G06F12/1009 ,  G06F21/55

Abstract: A memory, a data processing system comprising a memory, a method of operating a memory and a memory compiler apparatus and method of memory compilation are provided, which relate to a memory comprising data storage circuitry to store data values at data locations. Addressing circuitry is provided to access the data value at a storage location in dependence on a received address and readout circuitry to provide an output value in dependence on the accessed data value. The memory further comprises scrambling circuitry to select at least one of: a mapping between the address and the storage location; and a mapping between the data value and the output value, in dependence on a received scrambling value. The mapping between the address and the storage location and/or the data value and the output value can thus be easily and rapidly changed.

公开(公告)号：US09036427B2

公开(公告)日：2015-05-19

申请号：US13943029

申请日：2013-07-16

Applicant: ARM LIMITED

Inventor： Nicolaas Klarinus Johannes Van Winkelhoff ,  Ali Alaoui ,  Pierre Lemarchand ,  Bastien Jean Claude Aghetti

IPC: G11C16/04 ,  G11C7/24 ,  G11C8/20 ,  G11C16/22 ,  G11C7/22

CPC classification number: G11C7/24 ,  G11C7/22 ,  G11C8/20 ,  G11C16/22

Abstract: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal. Such an approach enables the security of a memory device to be improved, and in particular prevents hackers from taking advantage of data remanence effects, by ensuring that stored data is overwritten in an efficient, and clock independent, manner, triggered by assertion of an erase signal generated if a pulse-based control signal does not take it is expected form.

Abstract translation: 本发明提供了一种用于擦除存储器件中的数据的装置和方法，该存储器件包括存储器单元阵列，并被配置为从时钟信号进行操作。 该装置包括擦除电路，响应于在断言状态下的擦除信号的接收，以独立于与所述阵列的预定擦除区域内的每个存储器单元的时钟信号执行强制写入操作。 此外，擦除信号产生电路被配置为接收控制信号并且将所述擦除信号保持在无效状态，只要控制信号采取在脉冲之间具有至少预定的最小频率的脉冲信号的形式即可。 擦除信号产生电路还被配置为如果控制信号不采取所述脉冲信号的形式，则在所述断言状态下发出所述擦除信号。 这样一种方法可以改善存储器件的安全性，并且特别是通过确保存储的数据以有效和时钟独立的方式被覆盖而被防止黑客利用数据剩余效应 如果基于脉冲的控制信号不采用，则产生信号。

公开(公告)号：US08885429B1

公开(公告)日：2014-11-11

申请号：US13915918

申请日：2013-06-12

Applicant: ARM Limited

Inventor： Nicolaas Klarinus Johannes Van Winkelhoff ,  Pierre Lemarchand ,  Bastien Jean Claude Aghetti ,  Virgile Javerliac

IPC: G11C7/00 ,  G11C29/52

CPC classification number: G11C29/52 ,  G11C7/20 ,  G11C7/24 ,  G11C11/419 ,  G11C16/14 ,  G11C16/22

Abstract: A memory device including an array of memory cells arranged as a plurality of rows and columns. Write circuitry then controls a voltage level of the associated at least one bit line for each of the addressed memory cells to cause write data to be written into the addressed memory cells. In the presence of an asserted erase signal, a decoder circuitry's operation is modified such that it issues, independently of the clock signal, an asserted word line signal on the word line associated with each row in a predetermined erase region of the array. Further, the write circuitry's operation is modified so that it controls the voltage level of the associated at least one bit line for each memory cell in the predetermined erase region, in order to cause erase write data to be written into the memory cells of the predetermined erase region.

Abstract translation: 一种存储器件，包括布置成多个行和列的存储单元阵列。 然后，写入电路控制每个寻址的存储器单元的相关联的至少一个位线的电压电平，以使写入数据被写入寻址的存储单元。 在有断言的擦除信号的存在下，解码器电路的操作被修改，使得其独立于时钟信号发出在阵列的预定擦除区域中与每行相关联的字线上的断言的字线信号。 此外，修改写入电路的操作，使得其控制预定擦除区域中的每个存储器单元的相关联的至少一个位线的电压电平，以便将擦除写入数据写入到预定的擦除区域的存储器单元中 擦除区域。