公开(公告)号：US09490325B2

公开(公告)日：2016-11-08

申请号：US15055122

申请日：2016-02-26

Applicant: ASM IP Holding B.V.

Inventor： Keith Doran Weeks

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/267 ,  H01L29/78 ,  H01L21/67

CPC classification number: H01L29/1054 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/67207 ,  H01L29/267 ,  H01L29/7851

Abstract: Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.

公开(公告)号：US20150014816A1

公开(公告)日：2015-01-15

申请号：US14143719

申请日：2013-12-30

Applicant: ASM IP Holding B.V.

Inventor： Keith Doran Weeks ,  John Tolle ,  Matthew G. Goodman ,  Sandeep Mehta

IPC: H01L21/02 ,  H01L29/167 ,  H01L29/36 ,  H01L21/306

CPC classification number: H01L29/36 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32135

Abstract: A method of forming a semiconductor material incorporating an electrical dopant is disclosed. In one aspect, a method of incorporating dopant in a semiconductor film comprises forming a first semiconductor material incorporating the dopant at a first dopant concentration and preferentially etching a portion of the first semiconductor material, wherein etching leaves a first etched semiconductor material incorporating the dopant at a second dopant concentration higher than the first dopant concentration.

Abstract translation: 公开了一种形成掺有电掺杂剂的半导体材料的方法。 在一个方面，一种在半导体膜中掺入掺杂剂的方法包括以第一掺杂剂浓度形成掺入掺杂剂的第一半导体材料，并优先蚀刻第一半导体材料的一部分，其中蚀刻留下掺入掺杂剂的第一蚀刻半导体材料 第二掺杂剂浓度高于第一掺杂剂浓度。

公开(公告)号：US20160181368A1

公开(公告)日：2016-06-23

申请号：US15055122

申请日：2016-02-26

Applicant: ASM IP Holding B.V.

Inventor： Keith Doran Weeks

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/267

CPC classification number: H01L29/1054 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/67207 ,  H01L29/267 ,  H01L29/7851

Abstract: Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.

Abstract translation: 公开了包括拉伸应力硅砷层的结构，包括结构的器件以及形成器件和结构的方法。 示例性的拉伸应力硅砷层具有大于每立方厘米5E + 20个砷原子的砷掺杂水平。 该结构可用于形成金属氧化物半导体器件。

公开(公告)号：US09324811B2

公开(公告)日：2016-04-26

申请号：US14018345

申请日：2013-09-04

Applicant: ASM IP Holding B.V.

Inventor： Keith Doran Weeks

IPC: H01L21/336 ,  H01L29/267 ,  H01L21/02 ,  H01L29/10 ,  H01L21/67

CPC classification number: H01L29/1054 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/67207 ,  H01L29/267 ,  H01L29/7851

Abstract: Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.

Abstract translation: 公开了包括拉伸应力硅砷层的结构，包括结构的器件以及形成器件和结构的方法。 示例性的拉伸应力硅砷层具有大于每立方厘米5E + 20个砷原子的砷掺杂水平。 该结构可用于形成金属氧化物半导体器件。

公开(公告)号：US09099423B2

公开(公告)日：2015-08-04

申请号：US14143719

申请日：2013-12-30

Applicant: ASM IP HOLDING B.V.

Inventor： Keith Doran Weeks ,  John Tolle ,  Matthew G. Goodman ,  Sandeep Mehta

IPC: H01L29/36 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/36 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32135

Abstract: A method of forming a semiconductor material incorporating an electrical dopant is disclosed. In one aspect, a method of incorporating dopant in a semiconductor film comprises forming a first semiconductor material incorporating the dopant at a first dopant concentration and preferentially etching a portion of the first semiconductor material, wherein etching leaves a first etched semiconductor material incorporating the dopant at a second dopant concentration higher than the first dopant concentration.

Abstract translation: 公开了一种形成掺有电掺杂剂的半导体材料的方法。 在一个方面，一种在半导体膜中掺入掺杂剂的方法包括以第一掺杂剂浓度形成掺入掺杂剂的第一半导体材料，并优先蚀刻第一半导体材料的一部分，其中蚀刻留下掺入掺杂剂的第一蚀刻半导体材料 第二掺杂剂浓度高于第一掺杂剂浓度。

公开(公告)号：US20140084341A1

公开(公告)日：2014-03-27

申请号：US14018345

申请日：2013-09-04

Applicant: ASM IP Holding B.V.

Inventor： Keith Doran Weeks

IPC: H01L29/267 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/67207 ,  H01L29/267 ,  H01L29/7851

Abstract: Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.

Abstract translation: 公开了包括拉伸应力硅砷层的结构，包括结构的器件以及形成器件和结构的方法。 示例性的拉伸应力硅砷层具有大于每立方厘米5E + 20个砷原子的砷掺杂水平。 该结构可用于形成金属氧化物半导体器件。