公开(公告)号：US11814747B2

公开(公告)日：2023-11-14

申请号：US16849793

申请日：2020-04-15

申请人： ASM IP Holding B.V.

发明人： John Tolle ,  Joseph P. Margetis

IPC分类号： C30B31/16 ,  C30B25/14 ,  C30B25/16 ,  C30B25/18 ,  C30B25/08 ,  H01L21/67

CPC分类号： C30B25/14 ,  C30B25/08 ,  C30B25/16 ,  C30B25/18 ,  H01L21/67011

摘要： Gas-phase reactor systems and methods suitable for use with precursors that are solid phase at room temperature and pressure are disclosed. The systems and methods as described herein can be used to, for example, form amorphous, polycrystalline, or epitaxial layers (e.g., one or more doped semiconductor layers) on a surface of a substrate.

公开(公告)号：US11557474B2

公开(公告)日：2023-01-17

申请号：US16932275

申请日：2020-07-17

申请人： ASM IP Holding B.V.

发明人： John Tolle ,  Joe Margetis ,  David Kohen

IPC分类号： C23C16/30 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  C23C16/458 ,  C23C16/02 ,  C23C16/52 ,  C23C16/22 ,  C23C16/44 ,  C23C16/46 ,  C23C16/455

摘要： A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

公开(公告)号：US20210375622A1

公开(公告)日：2021-12-02

申请号：US17326912

申请日：2021-05-21

申请人： ASM IP Holding B.V.

发明人： Lucas Petersen Barbosa Lima ,  Joe Margetis ,  John Tolle ,  Rami Khazaka ,  Qi Xie

IPC分类号： H01L21/02 ,  C30B25/04 ,  C30B29/52 ,  C30B25/18

摘要： Methods and devices for epitaxially growing boron- and gallium-doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

公开(公告)号：US20190013199A1

公开(公告)日：2019-01-10

申请号：US15985261

申请日：2018-05-21

申请人： ASM IP Holding B.V.

发明人： Nupur Bhargava ,  Joe Margetis ,  John Tolle

IPC分类号： H01L21/02 ,  C23C16/40

摘要： A method for forming a forming a silicon germanium tin (SiGeSn) layer is disclosed. The method may include, providing a substrate within a reaction chamber, exposing the substrate to a pre-deposition precursor pulse, which comprises tin tetrachloride (SnCl4), exposing the substrate to a deposition precursor gas mixture comprising a hydrogenated silicon source, germane (GeH4), and tin tetrachloride (SnCl4), and depositing the silicon germanium tin (SiGeSn) layer over a surface of the substrate. Semiconductor device structures including a silicon germanium tin (SiGeSn) layer formed by the methods of the disclosure are also provided.

公开(公告)号：US09905420B2

公开(公告)日：2018-02-27

申请号：US14956115

申请日：2015-12-01

申请人： ASM IP Holding B.V.

发明人： Joe Margetis ,  John Tolle

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165

CPC分类号： H01L21/02535 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/161 ,  H01L29/165

摘要： Methods of forming silicon germanium tin (SixGe1-xSny) films are disclosed. Exemplary methods include growing films including silicon, germanium and tin in an epitaxial chemical vapor deposition reactor. Exemplary methods are suitable for high volume manufacturing. Also disclosed are structures and devices including silicon germanium tin films.

公开(公告)号：US09396934B2

公开(公告)日：2016-07-19

申请号：US13966782

申请日：2013-08-14

申请人： ASM IP Holding B.V.

发明人： John Tolle

IPC分类号： H01L21/02 ,  H01L29/161 ,  H01L29/165 ,  C30B25/18 ,  C30B29/52

CPC分类号： H01L21/02532 ,  C30B25/183 ,  C30B29/52 ,  H01L21/02535 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/161 ,  H01L29/165

摘要： Methods of forming germanium-tin films using germane as a precursor are disclosed. Exemplary methods include growing films including germanium and tin in an epitaxial chemical vapor deposition reactor, wherein a ratio of a tin precursor to germane is less than 0.1. Also disclosed are structures and devices including germanium-tin films formed using the methods described herein.

摘要翻译： 公开了使用锗烷作为前体形成锗 - 锡膜的方法。 示例性方法包括在外延化学气相沉积反应器中生长包括锗和锡的膜，其中锡前体与锗烷的比例小于0.1。 还公开了包括使用本文所述的方法形成的锗 - 锡膜的结构和装置。

公开(公告)号：US11901179B2

公开(公告)日：2024-02-13

申请号：US17509290

申请日：2021-10-25

申请人： ASM IP Holding B.V.

发明人： John Tolle ,  Robert Vyne

IPC分类号： H01L21/306 ,  H01L21/02 ,  H01J37/32 ,  C23C16/24 ,  C23C16/455 ,  C23C16/02

CPC分类号： H01L21/02532 ,  C23C16/0245 ,  C23C16/24 ,  C23C16/455 ,  H01J37/32449 ,  H01J37/32899 ,  H01L21/0262 ,  H01L21/02576 ,  H01L21/02579 ,  H01J37/32357 ,  H01J2237/332 ,  H01J2237/334

摘要： A method for forming a layer on a substrate includes providing a substrate in a reactor of a semiconductor processing system, the reactor having a divider separating an upper chamber from a lower chamber and a substrate holder therein, the substrate having upper and lower surfaces. The wafer is positioned within the reactor using the substrate holder such that the upper surface bounds the upper chamber, a silicon-containing gas is flowed through the upper chamber to deposit a layer of the upper surface, and a halogen-containing gas is flowed through the lower chamber to etch a deposited film on at least one wall bounding the lower chamber while flowing the silicon-containing gas through the upper chamber. Semiconductor processing systems are also described.

公开(公告)号：US11168395B2

公开(公告)日：2021-11-09

申请号：US16816078

申请日：2020-03-11

申请人： ASM IP Holding B.V.

发明人： Sonti Sreeram ,  John Tolle ,  Joe Margetis ,  Junwei Su

IPC分类号： C23C16/455

摘要： A flange, flange assembly, and reactor system including the flange and flange assembly are disclosed. An exemplary flange assembly includes heated and cooled sections to independently control temperatures of sections of the flange. Methods of using the flange, flange assembly and reactor system are also disclosed.

公开(公告)号：US10446393B2

公开(公告)日：2019-10-15

申请号：US15957565

申请日：2018-04-19

申请人： ASM IP Holding B.V.

发明人： Nupur Bhargava ,  John Tolle ,  Joe Margetis ,  Matthew Goodman ,  Robert Vyne

IPC分类号： H01L21/02 ,  H01L29/66 ,  C30B29/10 ,  C30B25/10 ,  C30B25/02 ,  C30B29/06 ,  C30B29/52

摘要： A method for forming a silicon-containing epitaxial layer is disclosed. The method may include, heating a substrate to a temperature of less than approximately 950° C. and exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source. The method may also include depositing a silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×1021 atoms per cubic centimeter.

公开(公告)号：US10388509B2

公开(公告)日：2019-08-20

申请号：US15627189

申请日：2017-06-19

申请人： ASM IP Holding B.V.

发明人： Joe Margetis ,  John Tolle

IPC分类号： H01L21/02 ,  H01L29/161 ,  H01L21/67 ,  H01L21/768

摘要： A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.