公开(公告)号：US10423745B2

公开(公告)日：2019-09-24

申请号：US14537441

申请日：2014-11-10

Applicant: ASML NETHERLANDS B.V.

Inventor： Hua-Yu Liu ,  Jiangwei Li ,  Luoqi Chen ,  Wei Liu ,  Jiong Jiang

IPC: G06F17/50 ,  G03F7/20

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare.

公开(公告)号：US09934350B2

公开(公告)日：2018-04-03

申请号：US14874134

申请日：2015-10-02

Applicant: ASML NETHERLANDS B.V.

Inventor： Hua-Yu Liu

IPC: G06F17/50 ,  G03F1/00 ,  G03F1/36 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/50 ,  G06F17/5009

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

公开(公告)号：US09183324B2

公开(公告)日：2015-11-10

申请号：US13888816

申请日：2013-05-07

Applicant: ASML NETHERLANDS B.V.

Inventor： Hua-Yu Liu

IPC: G06F17/50 ,  G03F1/00 ,  G03F1/36 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/50 ,  G06F17/5009

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract translation: 本发明涉及光刻设备和工艺，更具体地涉及用于共同优化用于光刻设备和工艺的照明源和掩模的工具。 根据某些方面，本发明通过从源和掩码优化中使用的全套剪辑智能地选择一小组关键设计模式来实现全芯片模式覆盖，同时降低计算成本。 仅对这些选择的模式执行优化以获得优化的源。 然后优化的源用于优化全芯片的掩模（例如使用OPC和可制造性验证），并比较处理窗口性能结果。 如果结果与传统的全芯片SMO相当，则过程结束，否则提供了各种方法来迭代地收敛成功的结果。