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公开(公告)号:US11982947B2
公开(公告)日:2024-05-14
申请号:US18070155
申请日:2022-11-28
Applicant: ASML Netherlands B.V.
Inventor: Sander Catharina Reinier Derks , Daniel Jozef Maria Direcks , Maurice Wilhelmus Leonardus Hendricus Feijts , Pieter Gerardus Mathijs Hoeijmakers , Katja Cornelia Joanna Clasina Moors , Violeta Navarro Paredes , William Peter Van Drent , Jan Steven Christiaan Westerlaken
CPC classification number: G03F7/70916 , G03F7/70033 , G03F7/70891 , H05G2/005 , H05G2/008
Abstract: A contamination trap for use in a debris mitigation system of a radiation source, the contamination trap comprising a plurality of vanes configured to trap fuel debris emitted from a plasma formation region of the radiation source; wherein at least one vane or each vane of the plurality of vanes comprises a material comprising a thermal conductivity above 30 W m−1 K−1.
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公开(公告)号:US11556067B2
公开(公告)日:2023-01-17
申请号:US17603687
申请日:2020-03-10
Applicant: ASML Netherlands B.V.
Inventor: Sander Catharina Reinier Derks , Daniel Jozef Maria Direcks , Maurice Wilhelmus Leonardus Hendricus Feijts , Pieter Gerardus Mathijs Hoeijmakers , Katja Cornelia Joanna Clasina Moors , Violeta Navarro Paredes , William Peter Van Drent , Jan Steven Christiaan Westerlaken
Abstract: A contamination trap for use in a debris mitigation system of a radiation source, the contamination trap comprising a plurality of vanes configured to trap fuel debris emitted from a plasma formation region of the radiation source; wherein at least one vane or each vane of the plurality of vanes comprises a material comprising a thermal conductivity above 30 W m−1K−1.
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公开(公告)号:US10018924B2
公开(公告)日:2018-07-10
申请号:US15014829
申请日:2016-02-03
Applicant: ASML NETHERLANDS B.V.
Inventor: Raymond Wilhelmus Louis Lafarre , Nicolaas Ten Kate , Nina Vladimirovna Dziomkina , Yogesh Pramod Karade , Siegfried Alexander Tromp , Jacobus Josephus Leijssen , Elisabeth Corinne Rodenburg , Maurice Wilhelmus Leonardus Hendricus Feijts , Hendrik Huisman
CPC classification number: G03F7/70716 , B05D3/02 , G01J5/0285 , G01J5/20 , G03F7/70341 , G03F7/70708
Abstract: A substrate holder for a lithographic apparatus has a planarization layer provided on a surface thereof. The planarization layer provides a smooth surface for the formation of a thin film stack forming an electronic component. The thin film stack comprises an (optional) isolation layer, a metal layer forming an electrode, a sensor, a heater, a transistor or a logic device, and a top isolation layer.
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