-
公开(公告)号:US20180268093A1
公开(公告)日:2018-09-20
申请号:US15982933
申请日:2018-05-17
Applicant: ASML Netherlands B.V.
Inventor: Guangqing CHEN , Shufeng Bai , Eric Richard Kent , Yen-Wen Lu , Paul Anthony Tuffy , Jen-Shiang Wang , Youping Zhang , Gertjan Zwartjes , Jan Wouter Bijlsma
CPC classification number: G06F17/5009 , G03F7/705 , G03F7/70633 , G03F7/70683 , G06F17/12 , G06F17/14 , G06F2217/12 , G06F2217/14
Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
-
公开(公告)号:US11875101B2
公开(公告)日:2024-01-16
申请号:US17616368
申请日:2020-05-25
Applicant: ASML NETHERLANDS B.V.
Inventor: Jen-Shiang Wang , Feng Chen , Matteo Alessandro Francavilla , Jan Wouter Bijlsma
IPC: G06F30/30 , G06F30/398 , G03F7/00 , G06F30/392 , G06F30/27 , G06F119/18
CPC classification number: G06F30/398 , G03F7/705 , G06F30/27 , G06F30/392 , G06F2119/18
Abstract: A patterning process modeling method includes determining, with a front end of a process model, a function associated with process physics and/or chemistry of an operation within a patterning process flow; and determining, with a back end of the process model, a predicted wafer geometry. The back end includes a volumetric representation of a target area on the wafer. The predicted wafer geometry is determined by applying the function from the front end to manipulate the volumetric representation of the wafer. The volumetric representation of the wafer may be generated using volumetric dynamic B-trees. The volumetric representation of the wafer may be manipulated using a level set method. The function associated with the process physics and/or chemistry of the operation within the patterning process flow may be a velocity/speed function. Incoming flux on a modeled surface of the wafer may be determined using ray tracing.
-
公开(公告)号:US10296681B2
公开(公告)日:2019-05-21
申请号:US15982933
申请日:2018-05-17
Applicant: ASML NETHERLANDS B.V.
Inventor: Guangqing Chen , Shufeng Bai , Eric Richard Kent , Yen-Wen Lu , Paul Anthony Tuffy , Jen-Shiang Wang , Youping Zhang , Gertjan Zwartjes , Jan Wouter Bijlsma
Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
-
公开(公告)号:US10007744B2
公开(公告)日:2018-06-26
申请号:US14941347
申请日:2015-11-13
Applicant: ASML NETHERLANDS B.V.
Inventor: Guangqing Chen , Shufeng Bai , Eric Richard Kent , Yen-Wen Lu , Paul Anthony Tuffy , Jen-Shiang Wang , Youping Zhang , Gertjan Zwartjes , Jan Wouter Bijlsma
CPC classification number: G06F17/5009 , G03F7/705 , G03F7/70633 , G03F7/70683 , G06F17/12 , G06F17/14 , G06F2217/12 , G06F2217/14
Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
-
-
-