公开(公告)号：US10057975B2

公开(公告)日：2018-08-21

申请号：US15703041

申请日：2017-09-13

Applicant: ASUSTeK COMPUTER INC.

Inventor： Hank Lin ,  Bin-Chyi Tseng ,  Chung-Han Tsai ,  Shih-Keng Chuang

IPC: H05K1/00 ,  H05K1/02 ,  H01R12/57 ,  H05K1/11 ,  H05K1/18 ,  H05K3/10 ,  H05K3/30 ,  H05K3/40

CPC classification number: H05K1/0213 ,  H01R12/57 ,  H01R12/724 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K3/10 ,  H05K3/306 ,  H05K3/40 ,  H05K2201/10022

Abstract: An electronic assembly and a method for manufacturing the electronic assembly are provided. The method includes: configuring a chip and a connector at a first wiring layer of a PCB, and determining a first trace between a first pin of the chip and a first pin of the connector, and a second trace between a second pin of the chip and a second pin of the connector according to a first internal resistance of the chip, a second internal resistance of the chip, a first internal resistance of the connector, and a second internal resistance of the connector.

公开(公告)号：US10461808B2

公开(公告)日：2019-10-29

申请号：US16132604

申请日：2018-09-17

Applicant: ASUSTeK COMPUTER INC.

Inventor： Hank Lin ,  Bin-Chyi Tseng ,  Tsung-Chieh Yen

IPC: H04B3/54 ,  H04B3/06

Abstract: A signal transmission assembly includes a substrate, a first transmission line, and a second transmission line. The first transmission line and the second transmission line are disposed on the substrate and extending along a first direction. The first transmission line comprises at least one first transmission section and at least one second transmission section. The first transmission section is apart from the second transmission line by a first distance. The second transmission section is apart from the second transmission line by a second distance. The first distance is greater than or equal to the second distance. A first edge of the first transmission section and a second edge of the second transmission section are proximal to the second transmission line and parallel to the first direction, and the second transmission line does not contact an edge extension line extending from the second edge along the first direction.

公开(公告)号：US10595395B2

公开(公告)日：2020-03-17

申请号：US15889694

申请日：2018-02-06

Applicant: ASUSTEK COMPUTER INC.

Inventor： Hank Lin ,  Bin-Chyi Tseng ,  Tsung-Chieh Yen

IPC: H05K1/02

Abstract: A circuit layout structure is provided. In the circuit layout structure, a transmission line group is disposed on a substrate. In its first differential signal transmission line pair, a first negative polarity transmission line is parallel to a first positive polarity transmission line and is configured to transmit a first negative polarity transmission signal of a first differential signal. In a second differential signal transmission line pair, a second positive polarity transmission line is parallel to a single-ended signal transmission line and is configured to transmit a second positive polarity transmission signal of a second differential signal. The second negative polarity transmission line is parallel to the second positive polarity transmission line. The single-ended signal transmission line is disposed between the first differential signal transmission line pair and the second differential signal transmission line pair.

公开(公告)号：US20180098415A1

公开(公告)日：2018-04-05

申请号：US15703041

申请日：2017-09-13

Applicant: ASUSTeK COMPUTER INC.

Inventor： Hank Lin ,  Bin-Chyi Tseng ,  Chung-Han Tsai ,  Shih-Keng Chuang

IPC: H05K1/02 ,  H01R12/57 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H05K3/40 ,  H05K3/10

CPC classification number: H05K1/0213 ,  H01R12/57 ,  H01R12/724 ,  H05K1/115 ,  H05K1/181 ,  H05K3/10 ,  H05K3/306 ,  H05K3/40 ,  H05K2201/10022

Abstract: An electronic assembly and a method for manufacturing the electronic assembly are provided. The method includes: configuring a chip and a connector at a first wiring layer of a PCB, and determining a first trace between a first pin of the chip and a first pin of the connector, and a second trace between a second pin of the chip and a second pin of the connector according to a first internal resistance of the chip, a second internal resistance of the chip, a first internal resistance of the connector, and a second internal resistance of the connector.