公开(公告)号：US11003588B2

公开(公告)日：2021-05-11

申请号：US16548692

申请日：2019-08-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sonu Arora ,  Paul Blinzer ,  Philip Ng ,  Nippon Harshadk Raval

IPC: G06F3/06 ,  G06F12/1027 ,  G06F13/16

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

公开(公告)号：US12056535B2

公开(公告)日：2024-08-06

申请号：US17137925

申请日：2020-12-30

Applicant: ATI Technologies ULC

Inventor： Indrani Paul ,  Leonardo De Paula Rosa Piga ,  Mahesh Subramony ,  Sonu Arora ,  Donald Cherepacha ,  Adam N C Clark

IPC: G06F9/50 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/505 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/5016 ,  G06F11/3037 ,  G06F11/3062 ,  G06F11/3409 ,  G06F2209/501 ,  G06F2209/508

Abstract: Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on an integrated circuit (IC), and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.

公开(公告)号：US20220206850A1

公开(公告)日：2022-06-30

申请号：US17137925

申请日：2020-12-30

Applicant: ATI Technologies ULC

Inventor： Indrani Paul ,  Leonardo De Paula Rosa Piga ,  Mahesh Subramony ,  Sonu Arora ,  Donald Cherepacha ,  Adam N. C. Clark

IPC: G06F9/50 ,  G06F11/30 ,  G06F1/3203

Abstract: Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on the IC, and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.