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公开(公告)号：US11507158B2
公开(公告)日：2022-11-22
申请号：US16872602
申请日：2020-05-12
IPC分类号： G06F1/26
摘要： Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the priority of a central processing unit component responsive to a central processing unit component's current usage data.
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公开(公告)号：US11886878B2
公开(公告)日：2024-01-30
申请号：US16712891
申请日：2019-12-12
发明人： Sukesh Shenoy , Adam N. C. Clark , Indrani Paul
IPC分类号： G06F1/00 , G06F9/30 , G06F9/48 , G06F1/3203 , G06F9/38
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/3877 , G06F9/4843 , G06F2009/3883
摘要： An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.
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公开(公告)号：US20220206850A1
公开(公告)日：2022-06-30
申请号：US17137925
申请日：2020-12-30
申请人： ATI Technologies ULC
发明人： Indrani Paul , Leonardo De Paula Rosa Piga , Mahesh Subramony , Sonu Arora , Donald Cherepacha , Adam N. C. Clark
IPC分类号： G06F9/50 , G06F11/30 , G06F1/3203
摘要： Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on the IC, and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.
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公开(公告)号：US09785218B2
公开(公告)日：2017-10-10
申请号：US14846058
申请日：2015-09-04
CPC分类号： G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/24 , Y02D50/20
摘要： A power management controller tracks the idle state of a compute unit and compares the tracked idle state with a first threshold. If the tracked idle state is above the first threshold a power state of the compute unit is limited to a low power state so that the power state does not rise due to activity that occurs in low utilization scenarios. The tracked idle state is compared to a second threshold and if the tracked idle state is below the second threshold, indicating that the compute unit is not in a low utilization scenario, a limit on the power state is removed and the power state of the compute unit is allowed to rise.
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