POWER VIA WITH REDUCED RESISTANCE
    3.
    发明公开

    公开(公告)号:US20240113022A1

    公开(公告)日:2024-04-04

    申请号:US17937313

    申请日:2022-09-30

    Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes, at a first node that receives a power supply reference, a first micro through silicon via (TSV) that traverses through a silicon substrate layer to a backside metal layer. The integrated circuit includes, at a second node that receives the power supply reference, a second micro TSV that physically contacts at least one source region. The integrated circuit includes a first power rail that connects the first micro TSV to the second micro TSV. This power rail replaces contacts between the micro TSVs and a second power rail such as the frontside metal zero (M0) layer. Each of the first power rail, the second power rail, and the backside metal layer provides power connection redundancy that increases charge sharing, improves wafer yield, and reduces voltage droop.

    ZERO DIFFUSION BREAK BETWEEN STANDARD CELLS USING THREE-DIMENSIONAL CROSS FIELD EFFECT SELF-ALIGNED TRANSISTORS

    公开(公告)号:US20240403529A1

    公开(公告)日:2024-12-05

    申请号:US18326835

    申请日:2023-05-31

    Abstract: An apparatus and method for efficiently creating layout of standard cells to improve floor planning of a chip. In various implementations, an integrated circuit uses multiple standard cells with an absence of diffusion breaks at cell boundaries. The standard cells use vertically stacked non-planer transistors. Multiple transistors are formed with an active region having a length between a source region and a drain region of a single transistor. Therefore, the active regions of these transistors are not formed across multiple gate terminals. By having active regions of these transistors formed across a single gate terminal of a single transistor, there is sufficient spacing to provide electrical isolation between two active regions of the two adjoining standard cells. This is true even when the two adjoining standard cells share a source/drain region at the cell boundaries. Accordingly, forming diffusion breaks at the edges of these standard cells can be skipped.

    METAL DENSITY DISTRIBUTION FOR DOUBLE PATTERN LITHOGRAPHY
    7.
    发明申请
    METAL DENSITY DISTRIBUTION FOR DOUBLE PATTERN LITHOGRAPHY 审中-公开
    金属密度分布的双模式图

    公开(公告)号:US20140145342A1

    公开(公告)日:2014-05-29

    申请号:US13686184

    申请日:2012-11-27

    Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.

    Abstract translation: 提供了方法,计算机可读介质和装置。 一种方法包括并且所述计算机可读介质被配置用于将整体图案分解为包括电力轨基座图案并进入第二掩模图案的第一掩模图案,并且在所述第二掩模图案上生成至少为电动轨迹插入图案 部分地与第一掩模图案的电源轨基座图案对准。 该装置通过使用通过该方法产生的光刻掩模的光刻制造。

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