公开(公告)号：US20180018419A1

公开(公告)日：2018-01-18

申请号：US15207691

申请日：2016-07-12

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Omid Rowhani ,  Ioan Cordos ,  Kerry Hamel ,  Donald Clay

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. The method also includes selecting a second cell from the standard cell library and placing the second cell at a second location of the physical layout such that a second edge of a cell boundary of the second cell abuts the first edge of the cell boundary of the first cell, and wherein the metal segment extends into a metal track at the metal layer of the second cell.

公开(公告)号：US09837398B1

公开(公告)日：2017-12-05

申请号：US15360168

申请日：2016-11-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Omid Rowhani ,  Jason P. Cain ,  Ioan Cordos ,  Michael Davinson Sherriff ,  Hoang Q. Dao

IPC: H01L27/118 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F17/5077 ,  H01L27/11807 ,  H01L2027/11875

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

公开(公告)号：US20240113022A1

公开(公告)日：2024-04-04

申请号：US17937313

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Richard T. Schultz ,  Omid Rowhani

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535 ,  H01L27/118

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L23/535 ,  H01L27/11807 ,  H01L2027/11887

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes, at a first node that receives a power supply reference, a first micro through silicon via (TSV) that traverses through a silicon substrate layer to a backside metal layer. The integrated circuit includes, at a second node that receives the power supply reference, a second micro TSV that physically contacts at least one source region. The integrated circuit includes a first power rail that connects the first micro TSV to the second micro TSV. This power rail replaces contacts between the micro TSVs and a second power rail such as the frontside metal zero (M0) layer. Each of the first power rail, the second power rail, and the backside metal layer provides power connection redundancy that increases charge sharing, improves wafer yield, and reduces voltage droop.

公开(公告)号：US09977854B2

公开(公告)日：2018-05-22

申请号：US15207691

申请日：2016-07-12

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Omid Rowhani ,  Ioan Cordos ,  Kerry Hamel ,  Donald Clay

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. The method also includes selecting a second cell from the standard cell library and placing the second cell at a second location of the physical layout such that a second edge of a cell boundary of the second cell abuts the first edge of the cell boundary of the first cell, and wherein the metal segment extends into a metal track at the metal layer of the second cell.

公开(公告)号：US20240403529A1

公开(公告)日：2024-12-05

申请号：US18326835

申请日：2023-05-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Richard Schultz ,  Omid Rowhani

IPC: G06F30/392 ,  G06F30/394 ,  H01L27/118

Abstract: An apparatus and method for efficiently creating layout of standard cells to improve floor planning of a chip. In various implementations, an integrated circuit uses multiple standard cells with an absence of diffusion breaks at cell boundaries. The standard cells use vertically stacked non-planer transistors. Multiple transistors are formed with an active region having a length between a source region and a drain region of a single transistor. Therefore, the active regions of these transistors are not formed across multiple gate terminals. By having active regions of these transistors formed across a single gate terminal of a single transistor, there is sufficient spacing to provide electrical isolation between two active regions of the two adjoining standard cells. This is true even when the two adjoining standard cells share a source/drain region at the cell boundaries. Accordingly, forming diffusion breaks at the edges of these standard cells can be skipped.

公开(公告)号：US10283437B2

公开(公告)日：2019-05-07

申请号：US13686184

申请日：2012-11-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Richard T. Schultz ,  Omid Rowhani ,  Charles P. Tung

IPC: G03F7/20 ,  H01L23/48 ,  H01L21/311 ,  G03F7/00

Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.

公开(公告)号：US20140145342A1

公开(公告)日：2014-05-29

申请号：US13686184

申请日：2012-11-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Richard T. Schultz ,  Omid Rowhani ,  Charles P. Tung

IPC: H01L21/3213 ,  H01L23/48

CPC classification number: H01L23/48 ,  G03F7/0035 ,  G03F7/70466 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.

Abstract translation: 提供了方法，计算机可读介质和装置。 一种方法包括并且所述计算机可读介质被配置用于将整体图案分解为包括电力轨基座图案并进入第二掩模图案的第一掩模图案，并且在所述第二掩模图案上生成至少为电动轨迹插入图案 部分地与第一掩模图案的电源轨基座图案对准。 该装置通过使用通过该方法产生的光刻掩模的光刻制造。