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    Phase interpolator based transmission clock control
    2.
    发明申请
    Phase interpolator based transmission clock control 失效
    基于相位插值器的传输时钟控制

    公开(公告)号：US20050286669A1

    公开(公告)日：2005-12-29

    申请号：US10876602

    申请日：2004-06-28

    申请人： Aaron Buchwald ,  Michael Le ,  Hui Wang ,  Howard Baumer ,  Pieter Vorenkamp

    发明人： Aaron Buchwald ,  Michael Le ,  Hui Wang ,  Howard Baumer ,  Pieter Vorenkamp

    IPC分类号： H04L7/00 ,  H04L25/20

    CPC分类号： H04L7/0091 ,  H04L7/0025 ,  H04L7/0029 ,  H04L25/20

    摘要： A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

    摘要翻译： 提供了一种用于基于相位插值器的传输时钟控制的系统和方法。 该系统包括具有耦合到主定时发生器和传输模块的相位插值器的发射机。 相位插值器还耦合到接收器插值器控制模块和/或外部插值器控制模块。 当系统以重复模式运行时，发射机相位插值器从接收器插值器控制模块接收控制信号。 发射机相位内插器使用信号将传输时钟同步到采样时钟。 当系统在测试模式下操作时，用户在外部插值器控制模块中定义传输数据简档。 外部内插器控制模块基于轮廓生成控制信号。 发射机相位内插器使用该信号来生成传输模块使用的传输时钟，以生成具有所需简档的数据流。

    Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase
    3.
    发明申请
    Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase 有权
    具有与接收时钟信号相锁相的发送时钟信号相位的方法和收发器系统

    公开(公告)号：US20110007785A1

    公开(公告)日：2011-01-13

    申请号：US12881108

    申请日：2010-09-13

    申请人： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    发明人： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    IPC分类号： H04B1/38

    CPC分类号： H03K5/135 ,  H04L7/0012 ,  H04L7/0091

    摘要： A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

    摘要翻译： 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

    Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase
    4.
    发明授权
    Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase 有权
    方法和收发机系统具有与接收时钟信号相锁相的发射时钟信号相位

    公开(公告)号：US07796682B2

    公开(公告)日：2010-09-14

    申请号：US12476207

    申请日：2009-06-01

    申请人： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    发明人： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

    IPC分类号： H04L25/20 ,  H04L7/00 ,  H04B1/38

    CPC分类号： H03K5/135 ,  H04L7/0012 ,  H04L7/0091

    摘要： A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

    摘要翻译： 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

    Verification and correction of 10GBASE-X lane routing between nodes
    5.
    发明授权
    Verification and correction of 10GBASE-X lane routing between nodes 有权
    节点之间的10GBASE-X通道路由的验证和校正

    公开(公告)号：US07668086B2

    公开(公告)日：2010-02-23

    申请号：US10667385

    申请日：2003-09-23

    申请人： Maurice Caldwell ,  Howard Baumer

    发明人： Maurice Caldwell ,  Howard Baumer

    IPC分类号： G01R31/38

    CPC分类号： H04L43/50

    摘要： In a network having a first node and a second node, a method of verifying a lane routing between the first node and the second node. The first node and the second node operate according to a protocol in which: (1) a character is converted to code groups, (2) each code group has a corresponding lane, and (3) the code groups are communicated across the lanes in a parallel manner. A first set of code groups is transmitted from the first node. Preferably, the first set of code groups is different from a set of code groups predefined by the protocol. A second set of code groups is received at the second node. The second set of code groups corresponds to the first set of code groups. A determination is made whether the second set of code groups matches the first set of code groups. An identity of the first set of code groups can be preprogrammed within the second node. Preferably, the first set of code groups has a different code group in each lane. Optionally, the lane routing between the first node and the second node is corrected if the second set of code groups mismatches the first set of code groups.

    摘要翻译： 在具有第一节点和第二节点的网络中，验证第一节点和第二节点之间的车道路由的方法。 第一节点和第二节点根据协议操作，其中：（1）将字符转换为码组，（2）每个码组具有相应的车道，（3）码组在车道上通过 平行的方式。 从第一节点发送第一组代码组。 优选地，第一组代码组不同于由协议预定义的一组代码组。 在第二节点处接收第二组代码组。 第二组代码组对应于第一组代码组。 确定第二组代码组是否与第一组代码组匹配。 可以在第二节点内对第一组代码组的身份进行预编程。 优选地，第一组代码组在每个通道中具有不同的代码组。 可选地，如果第二组代码组与第一组代码组不匹配，则校正第一节点和第二节点之间的通道路由。

    METHOD AND SYSTEM FOR PHYSICAL LAYER AGGREGATION
    7.
    发明申请
    METHOD AND SYSTEM FOR PHYSICAL LAYER AGGREGATION 有权
    物理层聚集方法与系统

    公开(公告)号：US20080095189A1

    公开(公告)日：2008-04-24

    申请号：US11866692

    申请日：2007-10-03

    申请人： Howard Frazier ,  Patricia Thaler ,  Ali Ghiasi ,  Howard Baumer

    发明人： Howard Frazier ,  Patricia Thaler ,  Ali Ghiasi ,  Howard Baumer

    IPC分类号： H04L12/56 ,  H03M13/47

    CPC分类号： H04L69/14 ,  Y02D50/30

    摘要： Aspects of a system for physical layer aggregation may include one or more switch ICs and/or physical (PHY) layer ICs that enable reception of data packets via a medium access control (MAC) layer protocol entity. Each of the received data packets may be fragmented into a plurality of fragment payloads. Each of the plurality of fragment payloads may be sent to a PHY layer protocol entity instance a physical layer protocol entity instance selected from a plurality of physical layer protocol entity instances.

    摘要翻译： 用于物理层聚合的系统的方面可以包括一个或多个开关IC和/或物理（PHY）层IC，其能够经由介质访问控制（MAC）层协议实体接收数据分组。 每个接收到的数据分组可以被分段成多个片段有效载荷。 多个片段有效载荷中的每一个可以被发送到PHY层协议实体实例，从多个物理层协议实体实例中选择的物理层协议实体实例。

    Verification and correction of 10GBASE-X lane routing between nodes
    8.
    发明申请
    Verification and correction of 10GBASE-X lane routing between nodes 有权
    节点之间的10GBASE-X通道路由的验证和校正

    公开(公告)号：US20050063310A1

    公开(公告)日：2005-03-24

    申请号：US10667385

    申请日：2003-09-23

    申请人： Maurice Caldwell ,  Howard Baumer

    发明人： Maurice Caldwell ,  Howard Baumer

    IPC分类号： H01T13/60 ,  H04L12/26

    CPC分类号： H04L43/50

    摘要： In a network having a first node and a second node, a method of verifying a lane routing between the first node and the second node. The first node and the second node operate according to a protocol in which: (1) a character is converted to code groups, (2) each code group has a corresponding lane, and (3) the code groups are communicated across the lanes in a parallel manner. A first set of code groups is transmitted from the first node. Preferably, the first set of code groups is different from a set of code groups predefined by the protocol. A second set of code groups is received at the second node. The second set of code groups corresponds to the first set of code groups. A determination is made whether the second set of code groups matches the first set of code groups. An identity of the first set of code groups can be preprogrammed within the second node. Preferably, the first set of code groups has a different code group in each lane. Optionally, the lane routing between the first node and the second node is corrected if the second set of code groups mismatches the first set of code groups.

    摘要翻译： 在具有第一节点和第二节点的网络中，验证第一节点和第二节点之间的车道路由的方法。 第一节点和第二节点根据协议操作，其中：（1）将字符转换为码组，（2）每个码组具有相应的车道，（3）码组在车道上通过 平行的方式。 从第一节点发送第一组代码组。 优选地，第一组代码组不同于由协议预定义的一组代码组。 在第二节点处接收第二组代码组。 第二组代码组对应于第一组代码组。 确定第二组代码组是否与第一组代码组匹配。 可以在第二节点内对第一组代码组的身份进行预编程。 优选地，第一组代码组在每个通道中具有不同的代码组。 可选地，如果第二组代码组与第一组代码组不匹配，则校正第一节点和第二节点之间的通道路由。

    Crosstalk emission management
    9.
    发明授权
    Crosstalk emission management 失效
    串扰排放管理

    公开(公告)号：US08428111B2

    公开(公告)日：2013-04-23

    申请号：US11799368

    申请日：2007-05-01

    申请人： Magesh Valliappan ,  Howard Baumer ,  Anthony Brewster ,  Vivek Telang

    发明人： Magesh Valliappan ,  Howard Baumer ,  Anthony Brewster ,  Vivek Telang

    IPC分类号： H03H7/30 ,  H03K5/159

    CPC分类号： H04L25/03343 ,  H04B3/143 ,  H04B3/32 ,  H04L25/03038

    摘要： Various embodiments are disclosed relating to crosstalk emission management. In an example embodiment, an amplitude of a main tap of a transmit equalizer may be determined to limit crosstalk emitted from a local channel to one or more other channels to be less than a threshold. A ratio of an amplitude of at least one secondary tap of the transmit equalizer to the amplitude of the main tap may be determined to provide equalization to the local channel.

    摘要翻译： 公开了与串扰发射管理相关的各种实施例。 在示例性实施例中，可以确定发射均衡器的主抽头的幅度以将从本地信道发射到一个或多个其他信道的串扰限制为小于阈值。 可以确定发射均衡器的至少一个次级抽头的幅度与主抽头的幅度的比率，以向本地信道提供均衡。

    Systems and methods for digital interface translation
    10.
    发明授权
    Systems and methods for digital interface translation 有权
    数字接口转换的系统和方法

    公开(公告)号：US08315272B2

    公开(公告)日：2012-11-20

    申请号：US12552240

    申请日：2009-09-01

    申请人： Howard Baumer

    发明人： Howard Baumer

    IPC分类号： H04L12/28

    CPC分类号： H04L27/32 ,  G09G3/2096 ,  G09G5/008 ,  G09G2320/0252 ,  G09G2370/04 ,  G09G2370/10 ,  G09G2370/12 ,  H04L25/14

    摘要： Systems and methods of digital interface translation are described. One embodiment of the invention includes multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard, an auxiliary channel input configured to receive an auxiliary data channel, and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard. In addition, the multilane to single lane digital interface translator is configured to decode the received data into data streams, and interleave the data streams to form packets, the multilane to single lane digital interface translator is configured to insert auxiliary data received via the auxiliary channel input and idle data between the packets to produce an output data stream that is rate matched to the second data rate, and the multilane to single lane digital interface translator is configured to encode the output data stream in accordance with the output digital interface standard.

    摘要翻译： 描述了数字接口转换的系统和方法。 本发明的一个实施例包括多个接收机通道，其中至少一个接收机通道被配置为以第一数据速率接收数据信道并根据输入数字接口标准进行编码，辅助信道输入被配置为接收辅助信道 数据信道和单个发射机通道，其被配置为以第二数据速率输出单个数据信道并根据输出数字接口标准进行编码。 另外，多路到单通道数字接口转换器被配置为将接收的数据解码成数据流，并且交织数据流以形成分组，多路到单通道数字接口转换器被配置为插入经由辅助通道接收的辅助数据 输入和空闲数据之间的数据，以产生与第二数据速率匹配的输出数据流，并且多路到单通道数字接口转换器被配置为根据输出数字接口标准对输出数据流进行编码。