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公开(公告)号：US20140007066A1
公开(公告)日：2014-01-02
申请号：US13538175
申请日：2012-06-29
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F9/45516 , G06F11/1405 , G06F2201/805
摘要： State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code; and maintaining a value indicative of a manner in which a second portion of the register in the first state is to be restored in connection with a state recovery from the optimized code.
摘要翻译： 披露了用于计算平台的状态恢复方法和装置。 一个示例性方法包括：将第一指令插入到优化的代码中，以使得在执行优化的代码的区域之前将第一状态的寄存器的第一部分保存到存储器; 并且保持指示与从优化代码的状态恢复相关联地恢复处于第一状态的寄存器的第二部分的方式的值。
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公开(公告)号：US09032381B2
公开(公告)日：2015-05-12
申请号：US13538175
申请日：2012-06-29
CPC分类号： G06F8/443 , G06F9/45516 , G06F11/1405 , G06F2201/805
摘要： State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code; and maintaining a value indicative of a manner in which a second portion of the register in the first state is to be restored in connection with a state recovery from the optimized code.
摘要翻译： 披露了用于计算平台的状态恢复方法和装置。 一个示例性方法包括：将第一指令插入到优化的代码中，以使得在执行优化的代码的区域之前将第一状态的寄存器的第一部分保存到存储器; 并且保持指示与从优化代码的状态恢复相关联地恢复处于第一状态的寄存器的第二部分的方式的值。
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3.发明申请SPECULATIVE MEMORY DISAMBIGUATION ANALYSIS AND OPTIMIZATION WITH HARDWARE SUPPORT 审中-公开具有硬件支持的分布式存储器分析与优化公开(公告)号：US20140189667A1
公开(公告)日：2014-07-03
申请号：US13730916
申请日：2012-12-29
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： Methods and apparatus to provide speculative memory disambiguation analysis and optimization with hardware support are described. In one embodiment, input code is analyzed to determine one or more memory locations to be accessed by the input program and output code is generated based on the input code and one or more assumptions about invariance of the one or more memory locations. The output code is generated also based on hardware transactional memory support and hardware dynamic disambiguation support. Other embodiments are also described.
摘要翻译： 描述了通过硬件支持提供推测性内存消歧分析和优化的方法和设备。 在一个实施例中，分析输入代码以确定要由输入程序访问的一个或多个存储器位置，并且基于输入代码和关于一个或多个存储器位置的不变性的一个或多个假设来生成输出代码。 输出代码也是基于硬件事务内存支持和硬件动态消歧支持而生成的。 还描述了其它实施例。
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4.发明申请HARDWARE PROFILING MECHANISM TO ENABLE PAGE LEVEL AUTOMATIC BINARY TRANSLATION 有权硬件配置机制启用页面级自动二进制翻译公开(公告)号：US20130311758A1
公开(公告)日：2013-11-21
申请号：US13993792
申请日：2012-03-30
申请人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
发明人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F8/40 , G06F8/52 , G06F9/3017 , G06F9/3842 , G06F9/4552 , G06F11/073 , G06F11/3616 , G06F11/3652
摘要： A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
摘要翻译： 通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。 运行期间的硬件标识内存中包含潜在优化指令的代码页。 硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。 当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。 代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。 然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。
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公开(公告)号：US10387324B2
公开(公告)日：2019-08-20
申请号：US13976846
申请日：2011-12-08
申请人： Paul Caprioli , Abhay S. Kanhere
发明人： Paul Caprioli , Abhay S. Kanhere
IPC分类号： G06F12/10 , G06F9/52 , G06F12/1027
摘要： An apparatus and method is described herein for providing structures to support software memory re-ordering within atomic sections of code. Upon a start or end of a critical section, speculative bits of a translation buffer are reset. When a speculative memory access causes an address translation of a virtual address to a physical address, the translation buffer is searched to determine if another entry (a different virtual address) includes the same physical address. And if another entry does include the same physical address, the speculative execution is failed to provide protection from invalid execution resulting from the memory re-ordering.
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公开(公告)号：US09417855B2
公开(公告)日：2016-08-16
申请号：US13995400
申请日：2011-09-30
CPC分类号： G06F8/40 , G06F8/456 , G06F8/51 , G06F9/30109 , G06F9/30185 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3877 , G06F9/3887 , G06F9/4552
摘要： A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.
摘要翻译： 微架构可以提供硬件和软件协同设计的动态二进制翻译。 微架构可以调用执行动态二进制转换的方法。 该方法可以包括执行针对第一指令集编译的原始软件代码，使用处理器硬件来检测软件代码中的热点并将控制传递给二进制翻译翻译器，确定用于翻译的热点区域，使用 第二指令集，将转换的代码放置在转换高速缓存中，从翻译的高速缓存中执行转换的代码，并且在转换的代码完成执行之后转换回原始软件代码。
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公开(公告)号：US09342284B2
公开(公告)日：2016-05-17
申请号：US14040077
申请日：2013-09-27
CPC分类号： G06F8/4442 , G06F8/4441 , G06F9/30181 , G06F9/3834 , G06F9/45516 , G06F11/3604
摘要： Mechanisms for reducing memory access violations are disclosed. Sets of instructions may be identified and the identified sets of instructions may be re-translated or optimized to generate other sets of instructions. Execution of the other sets of instructions is analyzed to determine whether additional memory access violations occur. When additional memory access violations occur, further sets of instructions may be generated or re-translation/optimization of instructions may be disabled.
摘要翻译： 公开了减少内存访问冲突的机制。 可以识别指令集，并且可以重新翻译或优化所识别的指令集以产生其他指令集。 分析执行其他指令集以确定是否发生附加的存储器访问冲突。 当发生额外的存储器访问冲突时，可以生成另外的指令集，或者可以禁用重新转换/优化指令。
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公开(公告)号：US20130262838A1
公开(公告)日：2013-10-03
申请号：US13435165
申请日：2012-03-30
IPC分类号： G06F9/30
CPC分类号： G06F8/52 , G06F9/3834 , G06F9/3857
摘要： A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.
摘要翻译： 提供了一种支持软件二进制翻译的内存消歧硬件的方法。 该方法包括展开要在处理器内执行的一组指令，该组指令具有多个存储器操作。 确定存储器操作的原始相对顺序。 然后，在软件中检测和识别可能的重排序问题。 重新排序问题是在第一存储器操作已经在存储器操作的原始顺序之前被重新排序并且相对于第二存储器操作而被重新排序的时候。 解决了重新排序问题，并且传达到处理器的存储器操作的相对顺序。
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9.发明授权Hardware profiling mechanism to enable page level automatic binary translation 有权硬件分析机制，实现页面级自动二进制翻译公开(公告)号：US09542191B2
公开(公告)日：2017-01-10
申请号：US13993792
申请日：2012-03-30
申请人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
发明人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
CPC分类号： G06F11/3466 , G06F8/40 , G06F8/52 , G06F9/3017 , G06F9/3842 , G06F9/4552 , G06F11/073 , G06F11/3616 , G06F11/3652
摘要： A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
摘要翻译： 通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。 运行期间的硬件标识内存中包含潜在优化指令的代码页。 硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。 当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。 代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。 然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。
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公开(公告)号：US20140095842A1
公开(公告)日：2014-04-03
申请号：US13630154
申请日：2012-09-28
IPC分类号： G06F9/302
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30032 , G06F9/3012 , G06F9/3887 , G06F9/3893
摘要： A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane.
摘要翻译： 由处理器执行向量减少指令以对数据元素阵列提供有效的减少操作。 处理器包括向量寄存器。 每个向量寄存器被分成多个通道，每个通道存储相同数量的数据元素。 处理器还包括执行电路，其接收向量减少指令，以使用缩减运算符将存储在源操作数中的数据元素的阵列减少到目标操作数的结果。 源操作数和目标操作数中的每一个都是向量寄存器之一。 响应于向量减少指令，执行电路将减法运算符应用于每个通道中的两个数据元素，并且当存在每个通道中的至少一个数据元素时，移位一个或多个剩余数据元素。
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