-
公开(公告)号：US20130262838A1
公开(公告)日：2013-10-03
申请号：US13435165
申请日：2012-03-30
IPC分类号： G06F9/30
CPC分类号： G06F8/52 , G06F9/3834 , G06F9/3857
摘要： A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.
摘要翻译： 提供了一种支持软件二进制翻译的内存消歧硬件的方法。 该方法包括展开要在处理器内执行的一组指令，该组指令具有多个存储器操作。 确定存储器操作的原始相对顺序。 然后，在软件中检测和识别可能的重排序问题。 重新排序问题是在第一存储器操作已经在存储器操作的原始顺序之前被重新排序并且相对于第二存储器操作而被重新排序的时候。 解决了重新排序问题，并且传达到处理器的存储器操作的相对顺序。
-
公开(公告)号：US08826257B2
公开(公告)日：2014-09-02
申请号：US13435165
申请日：2012-03-30
IPC分类号： G06F9/45
CPC分类号： G06F8/52 , G06F9/3834 , G06F9/3857
摘要： A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.
摘要翻译： 提供了一种支持软件二进制翻译的内存消歧硬件的方法。 该方法包括展开要在处理器内执行的一组指令，该组指令具有多个存储器操作。 确定存储器操作的原始相对顺序。 然后，在软件中检测和识别可能的重排序问题。 重新排序问题是在第一存储器操作已经在存储器操作的原始顺序之前被重新排序并且相对于第二存储器操作而被重新排序的时候。 解决了重新排序问题，并且传达到处理器的存储器操作的相对顺序。
-
3.发明申请HARDWARE PROFILING MECHANISM TO ENABLE PAGE LEVEL AUTOMATIC BINARY TRANSLATION 有权硬件配置机制启用页面级自动二进制翻译公开(公告)号：US20130311758A1
公开(公告)日：2013-11-21
申请号：US13993792
申请日：2012-03-30
申请人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
发明人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F8/40 , G06F8/52 , G06F9/3017 , G06F9/3842 , G06F9/4552 , G06F11/073 , G06F11/3616 , G06F11/3652
摘要： A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
摘要翻译： 通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。 运行期间的硬件标识内存中包含潜在优化指令的代码页。 硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。 当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。 代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。 然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。
-
4.发明授权Hardware profiling mechanism to enable page level automatic binary translation 有权硬件分析机制，实现页面级自动二进制翻译公开(公告)号：US09542191B2
公开(公告)日：2017-01-10
申请号：US13993792
申请日：2012-03-30
申请人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
发明人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
CPC分类号： G06F11/3466 , G06F8/40 , G06F8/52 , G06F9/3017 , G06F9/3842 , G06F9/4552 , G06F11/073 , G06F11/3616 , G06F11/3652
摘要： A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
摘要翻译： 通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。 运行期间的硬件标识内存中包含潜在优化指令的代码页。 硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。 当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。 代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。 然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。
-
5.发明申请System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions 有权用于提高连续事务记忆区域吞吐量的系统，方法和装置公开(公告)号：US20140156933A1
公开(公告)日：2014-06-05
申请号：US13691218
申请日：2012-11-30
申请人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
发明人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
IPC分类号： G06F12/08
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30043 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F11/1448 , G06F11/1469 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2201/84 , G06F2212/1016 , G06F2212/452 , G06F2212/507 , G06F2212/6042 , G06F2212/62 , G06F2212/621 , G06F2213/0026
摘要： Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.
摘要翻译： 描述了使用TM区域指示符（或颜色）来提高TM吞吐量的系统，装置和方法。 通过使用TM区域指标，年龄较小的TM区域可以在等待旧TM区域提交时，退出指令。
-
6.发明申请公开(公告)号：US20170097826A1
公开(公告)日：2017-04-06
申请号：US15382476
申请日：2016-12-16
申请人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
发明人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
IPC分类号： G06F9/38 , G06F9/46 , G06F12/084 , G06F9/30 , G06F12/0875
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30043 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F11/1448 , G06F11/1469 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2201/84 , G06F2212/1016 , G06F2212/452 , G06F2212/507 , G06F2212/6042 , G06F2212/62 , G06F2212/621 , G06F2213/0026
摘要： Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.
-
公开(公告)号：US09652234B2
公开(公告)日：2017-05-16
申请号：US13996352
申请日：2011-09-30
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3808 , G06F9/3877 , G06F9/3887
摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.
-
8.发明申请公开(公告)号：US20170097891A1
公开(公告)日：2017-04-06
申请号：US15382462
申请日：2016-12-16
申请人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
发明人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
IPC分类号： G06F12/0817 , G06F12/0842 , G06F9/38 , G06F11/14 , G06F9/46 , G06F9/30 , G06F12/084 , G06F12/0875
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30043 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F11/1448 , G06F11/1469 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2201/84 , G06F2212/1016 , G06F2212/452 , G06F2212/507 , G06F2212/6042 , G06F2212/62 , G06F2212/621 , G06F2213/0026
摘要： Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.
-
9.发明申请Instruction and Logic to Control Transfer in a Partial Binary Translation System 有权控制部分二进制翻译系统传输的指令和逻辑公开(公告)号：US20130305019A1
公开(公告)日：2013-11-14
申请号：US13996352
申请日：2011-09-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3808 , G06F9/3877 , G06F9/3887
摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.
摘要翻译： 可以由运行时转换层提供用于热代码页（例如，经常执行的代码页）的处理器特定的动态二进制转换的代码的动态优化。 可以提供一种方法来使用指令后备缓冲器（iTLB）来映射原始代码页和转换的代码页。 该方法可以包括从原始代码页获取指令，确定所提取的指令是否是新代码页的第一指令以及原始代码页是否已被弃用。 如果两个确定返回是，该方法还可以包括从转换的代码页获取下一个指令。 如果任一确定返回否，则该方法还可以包括解码指令并从原始代码页获取下一条指令。
-
公开(公告)号：US09672019B2
公开(公告)日：2017-06-06
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.025 秒)