公开(公告)号：US20180285158A1

公开(公告)日：2018-10-04

申请号：US15477026

申请日：2017-04-01

申请人： Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

发明人： Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC分类号： G06F9/50 ,  G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F1/32

摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300238A1

公开(公告)日：2018-10-18

申请号：US15488637

申请日：2017-04-17

申请人： Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

发明人： Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC分类号： G06F12/06

摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

公开(公告)号：US20180285191A1

公开(公告)日：2018-10-04

申请号：US15477050

申请日：2017-04-01

申请人： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Eric C. Samson ,  Joydeep Ray ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Ankur N. Shah ,  Altug Koker

发明人： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Eric C. Samson ,  Joydeep Ray ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Ankur N. Shah ,  Altug Koker

IPC分类号： G06F11/07

摘要： Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.