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    Memory arbiter with intelligent page gathering logic
    3.
    发明授权
    Memory arbiter with intelligent page gathering logic 有权

    公开(公告)号：US07051172B2

    公开(公告)日：2006-05-23

    申请号：US10932395

    申请日：2004-09-01

    申请人： Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

    发明人： Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G06F13/161 ,  G06F13/18

    摘要： Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

    CURRENT CHANGE MITIGATION POLICY FOR LIMITING VOLTAGE DROOP IN GRAPHICS LOGIC
    6.
    发明申请
    CURRENT CHANGE MITIGATION POLICY FOR LIMITING VOLTAGE DROOP IN GRAPHICS LOGIC 有权
    目前用于限制图形逻辑电压降低的缓解策略

    公开(公告)号：US20150091915A1

    公开(公告)日：2015-04-02

    申请号：US14040472

    申请日：2013-09-27

    申请人： Linda L. Hurd ,  Wenyin Fu ,  Josh B. Mastronarde ,  Pradeep K. Golconda ,  Shalini Sankar ,  Eric C. Samson

    发明人： Linda L. Hurd ,  Wenyin Fu ,  Josh B. Mastronarde ,  Pradeep K. Golconda ,  Shalini Sankar ,  Eric C. Samson

    IPC分类号： G06T1/20

    CPC分类号： G06F9/38 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/325 ,  Y02D10/126

    摘要： Methods and apparatus relating to a current change mitigation policy for limiting voltage droop in graphics logic are described. In an embodiment, logic inserts one or more bubbles in one or more Execution Unit (EU) logic pipelines or one or more sampler logic pipelines of a processor. The bubbles at least temporarily reduce execution of operations in one or more subsystems of the processor based at least partially on a comparison of a first value and one or more clamping threshold values. The first value is determined based at least partially on a summation of products of one or more event counts and dynamic capacitance weights for one or more subsystems of the processor. Other embodiments are also disclosed and claimed.

    摘要翻译： 描述了与用于限制图形逻辑中的电压下降的当前变化缓解策略有关的方法和装置。 在一个实施例中，逻辑在一个或多个执行单元（EU）逻辑管线或处理器的一个或多个采样器逻辑管线中插入一个或多个气泡。 至少部分地基于第一值和一个或多个钳位阈值的比较，气泡至少暂时地减少处理器的一个或多个子系统中的操作的执行。 至少部分地基于处理器的一个或多个子系统的一个或多个事件计数和动态电容权重的乘积的总和确定第一值。 还公开并要求保护其他实施例。

    Dual input lane reordering data buffer
    8.
    发明授权
    Dual input lane reordering data buffer 失效
    双输入通道重排序数据缓冲区

    公开(公告)号：US06510472B1

    公开(公告)日：2003-01-21

    申请号：US09405503

    申请日：1999-09-23

    申请人： Josh B. Mastronarde

    发明人： Josh B. Mastronarde

    IPC分类号： G06F1300

    CPC分类号： G06F13/4018

    摘要： A buffer circuit coupling an input bus having a first portion and a second portion to an output bus. Each of the first portion, the second portion, and the output bus carry data of a predetermined width. The buffer circuit comprises a first plurality of registers, a second plurality of registers, an unload counter, and a multiplexer. The first plurality of registers is coupled to store data from the first portion of the input bus. The second plurality of registers is coupled to store data from the second portion of the input bus and from a data order signal. The unload counter provides an unload count that selects one of the first plurality of registers and a corresponding one of the second plurality of registers. The multiplexer provides either the selected one of the first plurality of registers or the corresponding one of the second plurality of registers to the output bus. The multiplexer is responsive to the data order signal stored in the corresponding one of the second plurality of registers.

    摘要翻译： 一个将具有第一部分和第二部分的输入总线耦合到输出总线的缓冲电路。 第一部分，第二部分和输出总线中的每一个承载预定宽度的数据。 缓冲电路包括第一多个寄存器，第二多个寄存器，卸载计数器和多路复用器。 第一组多个寄存器被耦合以存储来自输入总线的第一部分的数据。 第二多个寄存器被耦合以从输入总线的第二部分和数据订单信号存储数据。 卸载计数器提供卸载计数，其选择第一多个寄存器中的一个和第二多个寄存器中的对应的一个。 复用器将第一多个寄存器中的所选择的一个或第二多个寄存器中的对应的一个寄存器提供给输出总线。 多路复用器响应存储在第二多个寄存器中对应的一个寄存器中的数据顺序信号。

    Memory arbiter with intelligent page gathering logic
    9.
    发明授权
    Memory arbiter with intelligent page gathering logic 失效
    具有智能页面采集逻辑的内存仲裁器

    公开(公告)号：US06792516B2

    公开(公告)日：2004-09-14

    申请号：US10033440

    申请日：2001-12-28

    申请人： Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

    发明人： Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

    IPC分类号： G06F1200

    CPC分类号： G06F13/161 ,  G06F13/18

    摘要： Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

    摘要翻译： 本发明的实施例提供了一种用于将芯片组和图形业务引导到系统存储器的存储器仲裁器。 页面一致性和优先级用于优化内存带宽利用率，并保证等时显示请求的延迟。 仲裁器还包含一种防止CPU请求饥饿较低优先级请求的机制。 因此，存储器仲裁器提供了一种简单易于验证的架构，防止CPU不利地挨饿低优先级代理，并利用宽限期和存储器页面检测来优化仲裁交换机，从而增加内存带宽利用率。

    Method and apparatus for improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cycles
    10.
    发明授权
    Method and apparatus for improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cycles 有权
    用于在图形翻译后备缓冲区高速缓存未命中获取循环期间改善系统存储器带宽利用的方法和装置

    公开(公告)号：US06593931B1

    公开(公告)日：2003-07-15

    申请号：US09452540

    申请日：1999-12-01

    申请人： Josh B. Mastronarde ,  Russell W. Dyer ,  Himanshu Sinha

    发明人： Josh B. Mastronarde ,  Russell W. Dyer ,  Himanshu Sinha

    IPC分类号： G06F1318

    CPC分类号： G06F13/1684 ,  G06F12/1027 ,  G06F2212/302

    摘要： An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first request path and a second request path. The memory controller further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The memory controller also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.

    摘要翻译： 公开了一种存储控制器的实施例，该存储器控制器在图形翻转后备缓冲器取回周期期间改善主存储器带宽利用率。 存储器控制器包括第一请求路径和第二请求路径。 存储器控制器还包括包括高速缓存的图形翻译后备缓冲器。 当从第一请求路径或从第二请求路径接收的图形存储器请求错过高速缓存时，图形翻译后备缓冲器向存储器接口发出地址提取请求。 存储器控制器还包括存储器仲裁器，其包括第一请求路径周期跟踪器和第二请求路径周期跟踪器。 当从第一请求路径接收到的图形存储器请求由于图形翻转后视缓冲器高速缓存未命中而停止时，存储器仲裁器允许从第二请求路径接收的请求被发布到存储器接口。