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公开(公告)号：US11995351B2
公开(公告)日：2024-05-28
申请号：US17515976
申请日：2021-11-01
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Joseph L Greathouse , Sean Keely , Alan D. Smith , Anthony Asaro , Ling-Ling Wang , Milind N Nemlekar , Hari Thangirala , Felix Kuehling
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0679 , G06F13/28
Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.
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公开(公告)号：US20230384947A1
公开(公告)日：2023-11-30
申请号：US18208639
申请日：2023-06-12
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Joseph L. Greathouse , Alan D. Smith , Francisco L. Duran , Felix Kuehling , Anthony Asaro
CPC classification number: G06F3/0619 , G06F3/064 , G06F12/0607 , G06F3/0659 , G06F3/0673 , G06F3/0644
Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
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公开(公告)号：US11100604B2
公开(公告)日：2021-08-24
申请号：US16263709
申请日：2019-01-31
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Jeffrey Gongxian Cheng , Ahmed M. Abdelkhalek , Yinan Jiang , Xingsheng Wan , Anthony Asaro , David Martinez Nieto
Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.
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公开(公告)号：US20200250787A1
公开(公告)日：2020-08-06
申请号：US16263709
申请日：2019-01-31
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Jeffrey Gongxian Cheng , Ahmed M. Abdelkhalek , Yinan Jiang , Xingsheng Wan , Anthony Asaro , David Martinez Nieto
Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.
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公开(公告)号：US20200042348A1
公开(公告)日：2020-02-06
申请号：US16050948
申请日：2018-07-31
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.
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Patent Agency Ranking
公开(公告)号：US10365824B2
公开(公告)日：2019-07-30
申请号：US15495296
申请日：2017-04-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Wade K. Smith , Anthony Asaro
IPC: G06F3/06 , G06F12/1009 , G06F12/1027
Abstract: Systems, apparatuses, and methods for migrating memory pages are disclosed herein. In response to detecting that a migration of a first page between memory locations is being initiated, a first page table entry (PTE) corresponding to the first page is located and a migration pending indication is stored in the first PTE. In one embodiment, the migration pending indication is encoded in the first PTE by disabling read and write permissions. If a translation request targeting the first PTE is received by the MMU and the translation request corresponds to a read request, a read operation is allowed to the first page. Otherwise, if the translation request corresponds to a write request, a write operation to the first page is blocked and a silent retry request is generated and conveyed to the requesting client.
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公开(公告)号：US20180173649A1
公开(公告)日：2018-06-21
申请号：US15385566
申请日：2016-12-20
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Rostyslav Kyrychynskyi , Anthony Asaro , Kostantinos Danny Christidis , Mark Fowler , Michael J. Mantor , Robert Scott Hartog
CPC classification number: G06F13/161 , G06F13/1673 , G06F13/4068
Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.
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公开(公告)号：US09910788B2
公开(公告)日：2018-03-06
申请号：US14861055
申请日：2015-09-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Philip J. Rogers , Benjamin T. Sander , Anthony Asaro
IPC: G06F12/121 , G06F12/0891 , G06F12/1081 , G06F13/28 , G06F12/12
CPC classification number: G06F12/121 , G06F12/0891 , G06F12/0895 , G06F12/1081 , G06F12/12 , G06F12/127 , G06F13/28 , G06F2212/656
Abstract: A processor device includes a cache and a memory storing a set of counters. Each counter of the set is associated with a corresponding block of a plurality of blocks of the cache. The processor device further includes a cache access monitor to, for each time quantum for a series of one or more time quanta, increment counter values of the set of counters based on accesses to the corresponding blocks of the cache. The processor device further includes a transfer engine to, after completion of each time quantum, transfer the counter values of the set of counters for the time quantum to a corresponding location in a system memory.
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9.发明申请MANAGING COHERENT MEMORY BETWEEN AN ACCELERATED PROCESSING DEVICE AND A CENTRAL PROCESSING UNIT 审中-公开管理加速处理装置与中央处理装置之间的相关记忆公开(公告)号：US20160364334A1
公开(公告)日：2016-12-15
申请号：US15246056
申请日：2016-08-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anthony Asaro , Kevin Normoyle , Mark Hummel
IPC: G06F12/0815 , G06F12/0804
CPC classification number: G06F12/0815 , G06F12/0804 , G06F12/0806 , G06F12/0835 , G06F12/0837 , G06F12/0848 , G06F2212/1021 , G06F2212/1024 , G06F2212/283 , G06F2212/608 , Y02D10/13
Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.
Abstract translation: 现有的多处理器计算系统通常具有不足的存储器一致性，因此不能有效地利用单独的存储器系统。 具体来说，CPU无法有效地写入内存块，然后除了有明确的同步之外，还可以对存储器进行GPU访问。 另外，由于GPU被迫静态分割其本身与CPU之间的存储器位置，所以现有的多处理器计算系统不能有效地利用单独的存储器系统。 本文所描述的实施例通过在GPU内接收到通知，CPU已经完成处理存储在相干存储器中的数据，并使CPU缓冲器中的数据无效，GPU已经从相干存储器完成处理来克服这些缺陷。 本文描述的实施例还包括通过使用探针滤波器来将GPU存储器动态地划分为相干存储器和本地存储器。
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公开(公告)号：US09448930B2
公开(公告)日：2016-09-20
申请号：US14833850
申请日：2015-08-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anthony Asaro , Kevin Normoyle , Mark Hummel
CPC classification number: G06F12/1036 , G06F12/0284 , G06F12/0646 , G06F12/08 , G06F12/10 , G06F12/109 , G06F2212/1012 , G06F2212/152 , G06F2212/656 , G06F2212/657
Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
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