公开(公告)号：US10037283B2

公开(公告)日：2018-07-31

申请号：US15235214

申请日：2016-08-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony J. Bybell ,  John M. King

IPC: G06F12/123 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F12/12 ,  G06F12/124 ,  G06F2212/1016 ,  G06F2212/684 ,  G06F2212/70

Abstract: Techniques for improving translation lookaside buffer (TLB) operation are disclosed. A particular entry of the TLB is to be updated with data associated with a large page size. The TLB updates replacement policy data for that TLB entry for that large page size to indicate that the TLB entry is not the least-recently-used. To prevent smaller pages from evicting the TLB entry for the large page size, the TLB also updates replacement policy data for that TLB entry for the smaller page size to indicate that the TLB entry is not the least-recently-used.

公开(公告)号：US20180113814A1

公开(公告)日：2018-04-26

申请号：US15850113

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony J. Bybell

IPC: G06F12/1027 ,  H04L12/741 ,  G06F12/0864 ,  H04L12/743 ,  G11C15/00 ,  G06F1/32

CPC classification number: G06F12/1027 ,  G06F1/3287 ,  G06F12/0842 ,  G06F12/0864 ,  G06F17/30982 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/657 ,  G06F2212/683 ,  G11C5/14 ,  G11C15/00 ,  G11C2207/2263 ,  H04L45/745 ,  H04L45/7457

Abstract: A method and apparatus for reducing dynamic power consumption in a multi-thread content-addressable memory (CAM) is described. The disclosed apparatus includes a first input configured to receive a first virtual address corresponding to a first thread, a second input configured to receive a second virtual address corresponding to a second thread, a register bank including a plurality of registers each configured to store a binary word mapped to one of a plurality of physical addresses, a first comparator bank including a first plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration and configured to determine whether a first match is present, and a second comparator bank including a second plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration and configured to determine whether a second match is present.

公开(公告)号：US20180046583A1

公开(公告)日：2018-02-15

申请号：US15235214

申请日：2016-08-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony J. Bybell ,  John M. King

IPC: G06F12/1027 ,  G06F12/123

CPC classification number: G06F12/1027 ,  G06F12/124 ,  G06F2212/1016 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: Techniques for improving translation lookaside buffer (TLB) operation are disclosed. A particular entry of the TLB is to be updated with data associated with a large page size. The TLB updates replacement policy data for that TLB entry for that large page size to indicate that the TLB entry is not the least-recently-used. To prevent smaller pages from evicting the TLB entry for the large page size, the TLB also updates replacement policy data for that TLB entry for the smaller page size to indicate that the TLB entry is not the least-recently-used.

公开(公告)号：US12039337B2

公开(公告)日：2024-07-16

申请号：US17032494

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. Cohen ,  Tzu-Wei Lin ,  Anthony J. Bybell ,  Bill Kai Chiu Kwan ,  Frank C. Galloway

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3804 ,  G06F9/30058 ,  G06F9/3822 ,  G06F9/3867

Abstract: A processor employs a plurality of fetch and decode pipelines by dividing an instruction stream into instruction blocks with identified boundaries. The processor includes a branch predictor that generates branch predictions. Each branch prediction corresponds to a branch instruction and includes a prediction that the corresponding branch is to be taken or not taken. In addition, each branch prediction identifies both an end of the current branch prediction window and the start of another branch prediction window. Using these known boundaries, the processor provides different sequential fetch streams to different ones of the plurality of fetch and decode states, which concurrently process the instructions of the different fetch streams, thereby improving overall instruction throughput at the processor.

公开(公告)号：US11907126B2

公开(公告)日：2024-02-20

申请号：US17116950

申请日：2020-12-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. Cohen ,  Tzu-Wei Lin ,  Anthony J. Bybell ,  Sudherssen Kalaiselvan ,  James Mossman

IPC: G06F9/38 ,  G06F12/0855

CPC classification number: G06F12/0855 ,  G06F9/3808 ,  G06F9/3814 ,  G06F2212/60

Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.

公开(公告)号：US09864700B1

公开(公告)日：2018-01-09

申请号：US15238920

申请日：2016-08-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony J. Bybell

IPC: G06F12/00 ,  G06F12/1027 ,  G11C15/00 ,  G06F12/0864 ,  G06F1/32 ,  H04L12/741 ,  H04L12/743 ,  G06F17/30

CPC classification number: G06F12/1027 ,  G06F1/3287 ,  G06F12/0842 ,  G06F12/0864 ,  G06F17/30982 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/657 ,  G06F2212/683 ,  G11C5/14 ,  G11C15/00 ,  G11C2207/2263 ,  H04L45/745 ,  H04L45/7457

Abstract: A method and apparatus for reducing dynamic power consumption in a multi-thread content-addressable memory is described. The apparatus includes a first input configured to receive a first virtual address corresponding to a first thread, a second input configured to receive a second virtual address corresponding to a second thread, a register bank including a plurality of registers each configured to store a binary word mapped to one of a plurality of physical addresses, a first comparator bank including a first plurality of comparators each coupled to an associated register of the plurality of registers in a fully-associative configuration, and a second comparator bank including a second plurality of comparators each coupled to an associated register of the plurality of registers in a fully-associative configuration. An input virtual address to each comparator bank maintains its previous value for when a corresponding thread is not selected.

公开(公告)号：US10146698B2

公开(公告)日：2018-12-04

申请号：US15850113

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony J. Bybell

IPC: G06F12/00 ,  G06F12/1027 ,  G06F1/32 ,  G06F12/0864 ,  G11C15/00 ,  H04L12/741 ,  H04L12/743 ,  G06F12/0842 ,  G11C5/14 ,  G06F17/30

Abstract: A method and apparatus for reducing dynamic power consumption in a multi-thread content-addressable memory (CAM) is described. The disclosed apparatus includes a first input configured to receive a first virtual address corresponding to a first thread, a second input configured to receive a second virtual address corresponding to a second thread, a register bank including a plurality of registers each configured to store a binary word mapped to one of a plurality of physical addresses, a first comparator bank including a first plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration and configured to determine whether a first match is present, and a second comparator bank including a second plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration and configured to determine whether a second match is present.