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    Dynamic remapping of virtual address ranges using remap vector
    1.
    发明授权
    Dynamic remapping of virtual address ranges using remap vector 有权

    公开(公告)号：US11307993B2

    公开(公告)日：2022-04-19

    申请号：US16200446

    申请日：2018-11-26

    申请人： ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    发明人： Anthony Asaro ,  Richard E. George

    IPC分类号： G06F11/07 ,  G06F11/36 ,  G06F9/30 ,  G06F12/1009

    摘要： For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.

    HARDWARE SUPPORT FOR CONVOLUTION OPERATIONS
    4.
    发明公开
    HARDWARE SUPPORT FOR CONVOLUTION OPERATIONS 审中-公开

    公开(公告)号：US20230206395A1

    公开(公告)日：2023-06-29

    申请号：US17565301

    申请日：2021-12-29

    申请人： Advanced Micro Devices, Inc.

    发明人： Michael Y. Chow ,  Vidyashankar Viswanathan ,  Richard E. George

    IPC分类号： G06T3/40 ,  G06F17/15

    CPC分类号： G06T3/4046 ,  G06F17/153

    摘要： A technique for performing convolution operations is disclosed. The technique includes performing a first convolution operation based on a first convolutional layer input image to generate at least a portion of a first convolutional layer output image; while performing the first convolution operation, performing a second convolution operation based on a second convolutional layer input image to generate at least a portion of a second convolutional layer output image, wherein the second convolutional layer input image is based on the first convolutional layer output image; storing the portion of the first convolutional layer output image in a first memory dedicated to storing image data for convolution operations; and storing the portion of the second convolutional layer output image in a second memory dedicated to storing image data for convolution operations.

    DISABLING SELECTED IP
    5.
    发明公开
    DISABLING SELECTED IP 审中-公开

    公开(公告)号：US20230206368A1

    公开(公告)日：2023-06-29

    申请号：US17565409

    申请日：2021-12-29

    申请人： Advanced Micro Devices, Inc.

    发明人： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

    IPC分类号： G06Q50/18

    CPC分类号： G06Q50/184 ,  G06Q2220/18

    摘要： A technique for operating a processing device is disclosed. The method includes configuring at least one switch to interconnect one or more selected IP to the processing device, receiving an activation signal associated with the at least one switch based on the one or more selected IP, in response to the activation signal, causing the at least one switch to disable connection to the one or more selected IP, and verifying access to the one or more selected IP is disabled.

    Flexible memory system
    6.
    发明授权
    Flexible memory system 有权

    公开(公告)号：US12067237B2

    公开(公告)日：2024-08-20

    申请号：US17565315

    申请日：2021-12-29

    申请人： Advanced Micro Devices, Inc.

    发明人： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

    IPC分类号： G06F3/06

    CPC分类号： G06F3/061 ,  G06F3/0644 ,  G06F3/0676 ,  G06F3/0677 ,  G06F3/0679

    摘要： A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.

    FLEXIBLE MEMORY SYSTEM
    8.
    发明公开
    FLEXIBLE MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230205420A1

    公开(公告)日：2023-06-29

    申请号：US17565315

    申请日：2021-12-29

    申请人： Advanced Micro Devices, Inc.

    发明人： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

    IPC分类号： G06F3/06

    CPC分类号： G06F3/061 ,  G06F3/0644 ,  G06F3/0676 ,  G06F3/0677 ,  G06F3/0679

    摘要： A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.