公开(公告)号：US12198295B2

公开(公告)日：2025-01-14

申请号：US17565301

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Y. Chow ,  Vidyashankar Viswanathan ,  Richard E. George

IPC: G06T3/40 ,  G06F17/15 ,  G06T3/4046

Abstract: A technique for performing convolution operations is disclosed. The technique includes performing a first convolution operation based on a first convolutional layer input image to generate at least a portion of a first convolutional layer output image; while performing the first convolution operation, performing a second convolution operation based on a second convolutional layer input image to generate at least a portion of a second convolutional layer output image, wherein the second convolutional layer input image is based on the first convolutional layer output image; storing the portion of the first convolutional layer output image in a first memory dedicated to storing image data for convolution operations; and storing the portion of the second convolutional layer output image in a second memory dedicated to storing image data for convolution operations.

公开(公告)号：US20230103054A1

公开(公告)日：2023-03-30

申请号：US17485186

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Vidyashankar Viswanathan

IPC: G06F1/3206 ,  G06F1/329

Abstract: Systems and methods are disclosed for reducing the power consumption of a system. Techniques are described that queue a message, sent by a source engine of the system, in a queue of a destination engine of the system that is in a sleep mode. Then, a priority level associated with the queued message is determined. If the priority level is at a maximum level, the destination engine is brought into an active mode. If the priority level is at an intermediate level, the destination engine is brought into an active mode when a time, associated with the intermediate level, has elapsed. When the destination engine is brought into an active mode it processes all messages accumulated in its queue in an order determined by their associated priority levels.

公开(公告)号：US12105139B2

公开(公告)日：2024-10-01

申请号：US17565284

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3183

CPC classification number: G01R31/287 ,  G01R31/2879 ,  G01R31/31718 ,  G01R31/318314

Abstract: A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.

公开(公告)号：US20230206395A1

公开(公告)日：2023-06-29

申请号：US17565301

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Y. Chow ,  Vidyashankar Viswanathan ,  Richard E. George

IPC: G06T3/40 ,  G06F17/15

CPC classification number: G06T3/4046 ,  G06F17/153

Abstract: A technique for performing convolution operations is disclosed. The technique includes performing a first convolution operation based on a first convolutional layer input image to generate at least a portion of a first convolutional layer output image; while performing the first convolution operation, performing a second convolution operation based on a second convolutional layer input image to generate at least a portion of a second convolutional layer output image, wherein the second convolutional layer input image is based on the first convolutional layer output image; storing the portion of the first convolutional layer output image in a first memory dedicated to storing image data for convolution operations; and storing the portion of the second convolutional layer output image in a second memory dedicated to storing image data for convolution operations.

公开(公告)号：US20230206368A1

公开(公告)日：2023-06-29

申请号：US17565409

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

IPC: G06Q50/18

CPC classification number: G06Q50/184 ,  G06Q2220/18

Abstract: A technique for operating a processing device is disclosed. The method includes configuring at least one switch to interconnect one or more selected IP to the processing device, receiving an activation signal associated with the at least one switch based on the one or more selected IP, in response to the activation signal, causing the at least one switch to disable connection to the one or more selected IP, and verifying access to the one or more selected IP is disabled.

公开(公告)号：US20240402907A1

公开(公告)日：2024-12-05

申请号：US18805083

申请日：2024-08-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

IPC: G06F3/06

Abstract: A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.

公开(公告)号：US12067237B2

公开(公告)日：2024-08-20

申请号：US17565315

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0644 ,  G06F3/0676 ,  G06F3/0677 ,  G06F3/0679

Abstract: A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.

公开(公告)号：US11775043B2

公开(公告)日：2023-10-03

申请号：US17485186

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Vidyashankar Viswanathan

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/329

CPC classification number: G06F1/3206 ,  G06F1/329

Abstract: Systems and methods are disclosed for reducing the power consumption of a system. Techniques are described that queue a message, sent by a source engine of the system, in a queue of a destination engine of the system that is in a sleep mode. Then, a priority level associated with the queued message is determined. If the priority level is at a maximum level, the destination engine is brought into an active mode. If the priority level is at an intermediate level, the destination engine is brought into an active mode when a time, associated with the intermediate level, has elapsed. When the destination engine is brought into an active mode it processes all messages accumulated in its queue in an order determined by their associated priority levels.

公开(公告)号：US20230205680A1

公开(公告)日：2023-06-29

申请号：US17564036

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard E. George ,  Vidyashankar Viswanathan ,  Michael Y. Chow

IPC: G06F11/36 ,  G06F11/34

CPC classification number: G06F11/3688 ,  G06F11/3457 ,  G06F11/3684 ,  G06F11/3692

Abstract: Methods and systems are disclosed for emulating, in a platform, the performance of a target platform. Techniques disclosed include receiving, by the platform, values of system features, associated with a target performance of the target platform; and setting, by the platform, one or more configuration knobs, based on the received values of system features, to match a performance of the platform to the target performance of the target platform.

公开(公告)号：US20230205420A1

公开(公告)日：2023-06-29

申请号：US17565315

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Vidyashankar Viswanathan ,  Richard E. George ,  Michael Y. Chow

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0644 ,  G06F3/0676 ,  G06F3/0677 ,  G06F3/0679

Abstract: A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.