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公开(公告)号：US20230198528A1
公开(公告)日：2023-06-22
申请号：US17557590
申请日：2021-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
CPC classification number: H03L7/0805 , H03L7/085
Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
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公开(公告)号：US20230195191A1
公开(公告)日：2023-06-22
申请号：US17559111
申请日：2021-12-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Kaushik Mazumdar , Miguel Rodriguez , Mikhail Rodionov , Stephen Victor Kosonocky
CPC classification number: G06F1/28 , H03K19/20 , H03K5/2472 , H03K3/037
Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.
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公开(公告)号：US11942953B2
公开(公告)日：2024-03-26
申请号：US17557590
申请日：2021-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
CPC classification number: H03L7/0805 , H03L7/085
Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
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公开(公告)号：US12055991B2
公开(公告)日：2024-08-06
申请号：US17559111
申请日：2021-12-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Kaushik Mazumdar , Miguel Rodriguez , Mikhail Rodionov , Stephen Victor Kosonocky
CPC classification number: G06F1/28 , H03K3/037 , H03K5/2472 , H03K19/20
Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.
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Patent Agency Ranking
公开(公告)号：US20240106438A1
公开(公告)日：2024-03-28
申请号：US18525071
申请日：2023-11-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Kaushik Mazumdar , Ashish Jain , Joyce Cheuk Wai Wong , Mikhail Rodionov
IPC: H03L7/08 , G01R19/165
CPC classification number: H03L7/08 , G01R19/16552
Abstract: An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.
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公开(公告)号：US20230144770A1
公开(公告)日：2023-05-11
申请号：US17521578
申请日：2021-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric J. Chapman , Stephen Victor Kosonocky , Kaushik Mazumdar , Vydhyanathan Kalyanasundharam , Samuel Naffziger , Eric M. Scott
IPC: G06F1/30
CPC classification number: G06F1/30
Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.
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公开(公告)号：US20230145626A1
公开(公告)日：2023-05-11
申请号：US17521601
申请日：2021-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Miguel Rodriguez , Stephen Victor Kosonocky , Kaushik Mazumdar
IPC: G01R31/40 , H03M3/00 , H03K5/24 , H03K19/0175
CPC classification number: G01R31/40 , H03M3/30 , H03K5/24 , H03K19/017509
Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.
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公开(公告)号：US11960340B2
公开(公告)日：2024-04-16
申请号：US17521578
申请日：2021-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric J. Chapman , Stephen Victor Kosonocky , Kaushik Mazumdar , Vydhyanathan Kalyanasundharam , Samuel Naffziger , Eric M. Scott
IPC: G06F1/30
CPC classification number: G06F1/30
Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.
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公开(公告)号：US11630161B1
公开(公告)日：2023-04-18
申请号：US17521601
申请日：2021-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Miguel Rodriguez , Stephen Victor Kosonocky , Kaushik Mazumdar
IPC: G01R31/40 , H03K19/0175 , H03K5/24 , H03M3/00
Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.
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