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公开(公告)号：US12055991B2
公开(公告)日：2024-08-06
申请号：US17559111
申请日：2021-12-22
CPC分类号： G06F1/28 , H03K3/037 , H03K5/2472 , H03K19/20
摘要： A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.
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公开(公告)号：US20230195191A1
公开(公告)日：2023-06-22
申请号：US17559111
申请日：2021-12-22
CPC分类号： G06F1/28 , H03K19/20 , H03K5/2472 , H03K3/037
摘要： A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.
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公开(公告)号：US20220091822A1
公开(公告)日：2022-03-24
申请号：US17028723
申请日：2020-09-22
摘要： A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.
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公开(公告)号：US10560022B2
公开(公告)日：2020-02-11
申请号：US16440838
申请日：2019-06-13
发明人： Wei Huang , Miguel Rodriguez , Karthik Rao
摘要： An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.
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公开(公告)号：US10248177B2
公开(公告)日：2019-04-02
申请号：US14919364
申请日：2015-10-21
IPC分类号： G06F1/32 , G06F1/30 , G06F1/26 , G06F1/3234 , G06F1/3287
摘要： A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply. One regulator is a global regulator while another is a local regulator found in each of the processing tiles. Processing tiles are grouped into two groups wherein one group includes tiles that may powered down to save power. Voltage rails of the two groups are selectively connected to equalize voltage levels when both groups are powered on and operating.
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公开(公告)号：US11630161B1
公开(公告)日：2023-04-18
申请号：US17521601
申请日：2021-11-08
IPC分类号： G01R31/40 , H03K19/0175 , H03K5/24 , H03M3/00
摘要： A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.
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公开(公告)号：US11573593B2
公开(公告)日：2023-02-07
申请号：US15954051
申请日：2018-04-16
摘要： A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.
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公开(公告)号：US11960854B2
公开(公告)日：2024-04-16
申请号：US17028723
申请日：2020-09-22
CPC分类号： G06F7/5443 , H03K21/08 , H03K19/20
摘要： A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.
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公开(公告)号：US20220206552A1
公开(公告)日：2022-06-30
申请号：US17134952
申请日：2020-12-28
IPC分类号： G06F1/30 , G06F1/3203 , G05F1/565
摘要： An integrated circuit includes a plurality of tiles receiving a power supply voltage, each having a corresponding analog circuit and operates in response to a first voltage, and a hardware controller receiving a voltage identification code and provides the first voltage to each of the plurality of tiles in response thereto. The hardware controller comprises a test time controller determining coefficients of a waveform that describes an average correspondence between the power supply voltage and the first voltage for the plurality of tiles, and a boot time controller determining a respective error signal indicating an error between the waveform and a respective actual waveform for each of the plurality of tiles, and providing the respective error signal to the corresponding analog circuit of each of the plurality of tiles. The corresponding analog circuit of each of the plurality of tiles adjusts the first voltage according to the respective error signal.
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10.发明申请公开(公告)号：US20190296644A1
公开(公告)日：2019-09-26
申请号：US16440838
申请日：2019-06-13
发明人： Wei Huang , Miguel Rodriguez , Karthik Rao
摘要： An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.
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