公开(公告)号：US20170287738A1

公开(公告)日：2017-10-05

申请号：US15628488

申请日：2017-06-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Hsuan TSAI ,  Chuehan HSIEH

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/3171 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/24137 ,  H01L2924/15311 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/3511

Abstract: A semiconductor device includes a first die including a first pad and a first passivation layer, a second die including a second pad and a second passivation layer, and an encapsulant surrounding the first die and the second die. Surfaces of the first die are not coplanar with corresponding surfaces of the second die. A dielectric layer covers at least portions of the first passivation layer and the second passivation layer, and further covers the encapsulant between the first die and the second die. The encapsulant has a first surface. The dielectric layer has a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant, and further has a third surface opposite the second surface. The semiconductor device further includes a redistribution layer electrically connected to the first pad and the second pad and disposed above the third surface of the dielectric layer.

公开(公告)号：US20210050273A1

公开(公告)日：2021-02-18

申请号：US16540837

申请日：2019-08-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ya-Yu HSIEH ,  Chin-Li KAO ,  Chung-Hsuan TSAI ,  Chia-Pin CHEN

IPC: H01L23/29 ,  H01L23/00 ,  H01L21/66 ,  H01L23/31

Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.

公开(公告)号：US20210272866A1

公开(公告)日：2021-09-02

申请号：US17322767

申请日：2021-05-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ya-Yu HSIEH ,  Chin-Li KAO ,  Chung-Hsuan TSAI ,  Chia-Pin CHEN

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L21/66

Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.

公开(公告)号：US20190267341A1

公开(公告)日：2019-08-29

申请号：US16413380

申请日：2019-05-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Hsuan TSAI

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package device includes: (1) a die having an active surface, a back surface opposite to the active surface and a lateral surface extending between the active surface and the back surface; (2) a first conductive pillar disposed on the active surface of the die and electrically connected to the die, the first conductive pillar having a top surface facing away from the die and a lateral surface substantially perpendicular to the top surface of the first conductive pillar; (3) a dielectric layer disposed on the active surface of the die and fully covering the lateral surface of the first conductive pillar; and (4) a package body encapsulating the back surface and the lateral surface of the die.

公开(公告)号：US20180308811A1

公开(公告)日：2018-10-25

申请号：US15495271

申请日：2017-04-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Hsuan TSAI

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L24/02 ,  H01L21/6835 ,  H01L23/3114 ,  H01L24/13 ,  H01L24/96 ,  H01L2221/68359 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025

Abstract: A semiconductor package device comprises a die, a dielectric layer, a plurality of conductive pillars and a package body. The die has an active surface, a back surface opposite to the active surface and a lateral surface extending between the active surface and the back surface. The dielectric layer is on the active surface of die, has a top surface and defines a plurality of openings. Each conductive pillar is disposed in a corresponding opening of the plurality of openings of the dielectric layer. Each conductive pillar is electrically connected to the die. Each conductive pillar has a top surface. The top surface of each conductive pillar is lower than the top surface of the dielectric layer. The package body encapsulates the back surface and the lateral surface of the die.

公开(公告)号：US20170025322A1

公开(公告)日：2017-01-26

申请号：US15287506

申请日：2016-10-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Hsuan TSAI ,  Chuehan HSIEH

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L23/3171 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/24137 ,  H01L2924/15311 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/3511

Abstract: A semiconductor device includes a first die including a first pad and a first passivation layer, a second die including a second pad and a second passivation layer, and an encapsulant surrounding the first die and the second die. Surfaces of the first die are not coplanar with corresponding surfaces of the second die. A dielectric layer covers at least portions of the first passivation layer and the second passivation layer, and further covers the encapsulant between the first die and the second die. The encapsulant has a first surface. The dielectric layer has a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant, and further has a third surface opposite the second surface. The semiconductor device further includes a redistribution layer electrically connected to the first pad and the second pad and disposed above the third surface of the dielectric layer.

Abstract translation: 半导体器件包括包括第一焊盘和第一钝化层的第一裸片，包括第二焊盘和第二钝化层的第二裸片以及包围第一裸片和第二裸片的密封剂。 第一管芯的表面不与第二管芯的相应表面共面。 电介质层覆盖第一钝化层和第二钝化层的至少一部分，并且还覆盖第一管芯和第二管芯之间的密封剂。 密封剂具有第一表面。 电介质层具有与第一钝化层相邻的第二表面，第二钝化层和密封剂，并且还具有与第二表面相对的第三表面。 半导体器件还包括电连接到第一焊盘和第二焊盘并设置在电介质层的第三表面之上的再分配层。

公开(公告)号：US20160218063A1

公开(公告)日：2016-07-28

申请号：US14605779

申请日：2015-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Hsuan TSAI ,  Chuehan HSIEH

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/3171 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/24137 ,  H01L2924/15311 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/3511

Abstract: Described herein is a semiconductor device and the manufacturing method thereof, wherein the semiconductor device includes a first die including a first pad and a first passivation layer; a second die including a second pad and a second passivation layer; an encapsulant surrounding the first die and the second die and comprising a first surface; a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer includes: a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant; and a third surface opposite to the second surface; and a redistribution layer electrically connecting to the first pad and the second pad and disposed above the third surface of the dielectric layer.

Abstract translation: 这里描述的是半导体器件及其制造方法，其中半导体器件包括：第一裸片，其包括第一焊盘和第一钝化层; 包括第二焊盘和第二钝化层的第二裸片; 围绕所述第一管芯和所述第二管芯并包括第一表面的密封剂; 介电层，其覆盖所述第一钝化层的至少一部分和所述第二钝化层的至少一部分，并进一步覆盖所述第一管芯和所述第二管芯之间的所述密封剂，其中所述电介质层包括：与所述第二钝化层相邻的第二表面 第一钝化层，第二钝化层和密封剂; 和与第二表面相对的第三表面; 以及再分配层，其电连接到第一焊盘和第二焊盘，并且设置在电介质层的第三表面之上。