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公开(公告)号:US09997484B2
公开(公告)日:2018-06-12
申请号:US15252139
申请日:2016-08-30
发明人: Takeori Maeda , Masatoshi Fukuda , Ryoji Matsushima , Hideo Aoki
CPC分类号: H01L24/17 , H01L21/56 , H01L23/3142 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/1319 , H01L2224/1403 , H01L2224/14133 , H01L2224/14505 , H01L2224/14517 , H01L2224/16145 , H01L2224/16227 , H01L2224/1712 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2924/0665 , H01L2924/0635
摘要: A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.
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公开(公告)号:US20180076156A1
公开(公告)日:2018-03-15
申请号:US15468606
申请日:2017-03-24
发明人: Byoung Chan KIM , Yong Ho BAEK
IPC分类号: H01L23/00 , H01L23/31 , H01L23/29 , H01L25/065
CPC分类号: H01L24/02 , H01L23/293 , H01L23/3178 , H01L24/17 , H01L25/0657 , H01L2224/02373 , H01L2224/02379 , H01L2224/1712 , H01L2225/06513 , H01L2225/06548 , H01L2225/06582
摘要: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed on the first interconnection member, an active surface of the memory chip, and an active surface of the processor chip. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to connection pads of the processor chip and connection pads of the memory chip, and the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member.
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公开(公告)号:US20180012856A1
公开(公告)日:2018-01-11
申请号:US15202195
申请日:2016-07-05
发明人: Deog Soon Choi , Ah Ron Lee , Hyon Mo Ku
IPC分类号: H01L23/00 , H01L23/498
CPC分类号: H01L24/09 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/81 , H01L2224/03828 , H01L2224/05554 , H01L2224/05555 , H01L2224/0912 , H01L2224/0951 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/1147 , H01L2224/1181 , H01L2224/1183 , H01L2224/11849 , H01L2224/119 , H01L2224/13007 , H01L2224/13014 , H01L2224/13016 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/1411 , H01L2224/1712 , H01L2224/175 , H01L2224/81192 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81815 , H05K3/34 , H01L2924/014 , H01L2924/0665 , H01L2924/00014 , H01L2924/00012
摘要: A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of pads disposed on the first face of the substrate, each of the plurality of pads including a first face and an opposing second face that is in contact with the first face of the substrate. The semiconductor package is further described to include a plurality of solder-on-pad structures provided on a first of the plurality of pads.
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公开(公告)号:US20170162509A1
公开(公告)日:2017-06-08
申请号:US15438321
申请日:2017-02-21
申请人: Intel Corporation
发明人: Mihir K. Roy , Mathew J. Manusharow
IPC分类号: H01L23/538 , H01L21/48 , H01L23/00 , H01L25/065 , H01L25/00 , H01L25/18
CPC分类号: H01L23/5386 , H01L21/4853 , H01L21/4857 , H01L23/13 , H01L23/147 , H01L23/5381 , H01L23/5383 , H01L23/5385 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/25 , H01L24/81 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L2224/13101 , H01L2224/1412 , H01L2224/14505 , H01L2224/16225 , H01L2224/16238 , H01L2224/1712 , H01L2224/24146 , H01L2224/2541 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/81986 , H01L2924/12042 , H01L2924/1432 , H01L2924/14335 , H01L2924/1434 , H01L2924/15153 , H01L2924/15747 , H01L2924/381 , H01L2924/014 , H01L2924/00014 , H01L2924/00
摘要: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
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公开(公告)号:US09484307B2
公开(公告)日:2016-11-01
申请号:US14605779
申请日:2015-01-26
发明人: Chung-Hsuan Tsai , Chuehan Hsieh
IPC分类号: H01L23/04 , H01L23/538 , H01L23/31 , H01L23/00 , H01L25/065
CPC分类号: H01L23/3171 , H01L21/486 , H01L21/568 , H01L23/3107 , H01L23/3114 , H01L23/3135 , H01L23/49534 , H01L23/49541 , H01L23/5386 , H01L23/5389 , H01L24/05 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/0655 , H01L2224/04105 , H01L2224/08137 , H01L2224/12105 , H01L2224/16227 , H01L2224/1712 , H01L2224/24137 , H01L2924/15311 , H01L2924/1811 , H01L2924/1815 , H01L2924/3511
摘要: Described herein is a semiconductor device and the manufacturing method thereof, wherein the semiconductor device includes a first die including a first pad and a first passivation layer; a second die including a second pad and a second passivation layer; an encapsulant surrounding the first die and the second die and comprising a first surface; a dielectric layer covering at least a portion of the first passivation layer and at least a portion of the second passivation layer, and further covering the encapsulant between the first die and the second die, wherein the dielectric layer includes: a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant; and a third surface opposite to the second surface; and a redistribution layer electrically connecting to the first pad and the second pad and disposed above the third surface of the dielectric layer.
摘要翻译: 这里描述的是半导体器件及其制造方法,其中半导体器件包括:第一裸片,其包括第一焊盘和第一钝化层; 包括第二焊盘和第二钝化层的第二裸片; 围绕所述第一管芯和所述第二管芯并包括第一表面的密封剂; 介电层,其覆盖所述第一钝化层的至少一部分和所述第二钝化层的至少一部分,并进一步覆盖所述第一管芯和所述第二管芯之间的所述密封剂,其中所述电介质层包括:与所述第二钝化层相邻的第二表面 第一钝化层,第二钝化层和密封剂; 和与第二表面相对的第三表面; 以及再分配层,其电连接到第一焊盘和第二焊盘,并且设置在电介质层的第三表面之上。
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公开(公告)号:US09275967B2
公开(公告)日:2016-03-01
申请号:US14148482
申请日:2014-01-06
发明人: Yu-Min Liang , Jiun-Yi Wu
CPC分类号: H01L23/49838 , H01L22/14 , H01L23/481 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L24/02 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/11614 , H01L2224/11622 , H01L2224/131 , H01L2224/13144 , H01L2224/13294 , H01L2224/133 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2224/1712 , H01L2224/17132 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81466 , H01L2224/81815 , H01L2924/01057 , H01L2924/01072 , H01L2924/05042 , H01L2924/0533 , H01L2924/0534 , H01L2924/05342 , H01L2924/05432 , H01L2924/05442 , H01L2924/05994 , H01L2924/14 , H01L2924/1531 , H01L2924/15787 , H01L2924/2064 , H01L2924/20641 , H05K1/0268 , H05K1/113 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/096 , H05K2201/0989 , H05K2201/10674 , H05K2203/0353 , H01L2924/014 , H01L2924/00014
摘要: A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.
摘要翻译: 提供了一个管芯和一个衬底。 芯片包括至少一个集成电路芯片,并且该基板包括至少部分延伸穿过其中的导电柱的第一和第二子集。 导电柱的第一子集中的每一个包括从衬底的表面突出的突出隆起焊盘,并且导电柱的第二子集各自部分地形成凹陷在衬底的表面内的迹线。 裸片经由多个导电凸块耦合到基板,每个导电凸块在突起凸块焊盘和模具中的一个之间延伸。
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公开(公告)号:US20150380328A1
公开(公告)日:2015-12-31
申请号:US14845786
申请日:2015-09-04
发明人: Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
CPC分类号: H01L22/32 , H01L22/14 , H01L22/30 , H01L22/34 , H01L23/544 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2223/54406 , H01L2223/5442 , H01L2223/54426 , H01L2223/54433 , H01L2223/54473 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/17051 , H01L2224/1712 , H01L2224/81193 , H01L2225/06596
摘要: A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component.
摘要翻译: 包装组件包括堆叠探针单元,其包括第一类型连接器和连接到第一类型连接器的第二类型连接器。 第一型连接器和第二型连接器通过封装部件的表面露出。
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公开(公告)号:US08476768B2
公开(公告)日:2013-07-02
申请号:US13170210
申请日:2011-06-28
申请人: Ajay Kumar , Sahil S. Dabare , Ajay K. Gaite , Shyam S. Gupta
发明人: Ajay Kumar , Sahil S. Dabare , Ajay K. Gaite , Shyam S. Gupta
IPC分类号: H01H79/00
CPC分类号: H01L23/50 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/0612 , H01L2224/06515 , H01L2224/16225 , H01L2224/1712 , H01L2224/48 , H01L2224/4912 , H01L2924/00014 , H01L2924/181 , H01L2924/3862 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要: A system on a chip (SOC) includes a physical interface having first and second sets of interface pads. Interface pads from the first set are interleaved with interface pads from the second set. Additionally, the SOC is arranged for operation with a superset die having first and second personalities and has a physical interface with interface pads. The SOC uses a first number of interface pads in the first personality and a second number of interface pads in the second personality, where the first number is greater than the second number. A switch switches signals between the superset die and the physical interface and, in the second personality, switches signals to the physical interface so that interface pads in the second number of interface pads are interleaved with interface pads not in use in the second personality.
摘要翻译: 芯片上的系统(SOC)包括具有第一和第二组接口焊盘的物理接口。 来自第一组的接口焊盘与来自第二组的接口焊盘交错。 另外,SOC被配置为具有具有第一和第二个性的超级管芯的操作,并且具有与接口焊盘的物理接口。 SOC使用第一个人中的第一数量的接口焊盘和第二个人中的第二数量的接口焊盘,其中第一个数量大于第二个数量。 A开关在超级管芯和物理接口之间切换信号,并且在第二个性中将信号切换到物理接口,使得第二数量的接口焊盘中的接口焊盘与不在第二个性中使用的接口焊盘交错。
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公开(公告)号:US20120098120A1
公开(公告)日:2012-04-26
申请号:US12908946
申请日:2010-10-21
申请人: Chen-Hua Yu , Hao-Yi Tsai , Jiun Yi Wu , Tin-Hao Kuo
发明人: Chen-Hua Yu , Hao-Yi Tsai , Jiun Yi Wu , Tin-Hao Kuo
CPC分类号: H01L24/16 , H01L24/13 , H01L24/17 , H01L2224/02377 , H01L2224/0401 , H01L2224/05553 , H01L2224/05567 , H01L2224/13012 , H01L2224/13014 , H01L2224/13022 , H01L2224/1308 , H01L2224/13082 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2224/1601 , H01L2224/16104 , H01L2224/16105 , H01L2224/16237 , H01L2224/1712 , H01L2224/81191 , H01L2224/81385 , H01L2224/81424 , H01L2224/81447 , H01L2924/14 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0103 , H01L2924/01025 , H01L2924/00012 , H01L2924/00
摘要: A low-stress chip package is disclosed. The package includes two substrates. The first substrate includes an array of first conductive structures in the corner area of the chip, and an array of second conductive structures in the peripheral edge area of the chip. The first and second conductive structures each has a conductive pillar having elongated cross section in the plane parallel to the first substrate and a solder bump over the pillar. The package also includes a second substrate having an array of metal traces. The elongated pillars each form a coaxial bump-on-trace interconnect with a metal trace respectively. The long axis of the elongated cross section of a pillar in the corner area of the chip points to chip's center area, and the long axis of the elongated cross section of a pillar in chip's peripheral edge area aligns perpendicular to the edge.
摘要翻译: 公开了一种低应力芯片封装。 该封装包括两个基板。 第一衬底包括在芯片的拐角区域中的第一导电结构的阵列和芯片的周边边缘区域中的第二导电结构的阵列。 第一和第二导电结构各自具有在与第一基板平行的平面中具有细长横截面的导电柱和在柱上的焊料凸块。 该封装还包括具有金属迹线阵列的第二衬底。 细长的柱分别与金属迹线形成同轴的跟踪轨迹互连。 芯片角部区域中的柱的细长截面的长轴指向芯片的中心区域,并且芯片的周缘区域中的柱的细长截面的长轴与边缘垂直排列。
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公开(公告)号:US09972590B2
公开(公告)日:2018-05-15
申请号:US15202195
申请日:2016-07-05
发明人: Deog Soon Choi , Ah Ron Lee , Hyun-Mo Ku
IPC分类号: H01L23/52 , H01L23/00 , H01L23/498
CPC分类号: H01L24/09 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/81 , H01L2224/03828 , H01L2224/05554 , H01L2224/05555 , H01L2224/0912 , H01L2224/0951 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/1147 , H01L2224/1181 , H01L2224/1183 , H01L2224/11849 , H01L2224/119 , H01L2224/13007 , H01L2224/13014 , H01L2224/13016 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/1411 , H01L2224/1712 , H01L2224/175 , H01L2224/81192 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81815 , H05K3/34 , H01L2924/014 , H01L2924/0665 , H01L2924/00014 , H01L2924/00012
摘要: A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of pads disposed on the first face of the substrate, each of the plurality of pads including a first face and an opposing second face that is in contact with the first face of the substrate. The semiconductor package is further described to include a plurality of solder-on-pad structures provided on a first of the plurality of pads.
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