公开(公告)号：US11848143B2

公开(公告)日：2023-12-19

申请号：US17065482

申请日：2020-10-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yunghsun Chen ,  Huang-Hsien Chang ,  Shao Hsuan Chuang

IPC: H01F27/24 ,  H01F27/28 ,  H01F27/40 ,  H01F41/04 ,  H01G4/30

CPC classification number: H01F27/2804 ,  H01F27/24 ,  H01F27/40 ,  H01F41/041 ,  H01G4/30

Abstract: An electronic device and a method for manufacturing an electronic device are provided. The electronic device includes an inductor. The inductor includes a plurality of line portions and a plurality of plate portions connected to the plurality of line portions. The line portions and the plate portions form a coil concentric to a horizontal axis.

公开(公告)号：US10741483B1

公开(公告)日：2020-08-11

申请号：US16774161

申请日：2020-01-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Syu-Tang Liu ,  Tsung-Tang Tsai ,  Huang-Hsien Chang ,  Ching-Ju Chen

IPC: H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.

公开(公告)号：US11631734B2

公开(公告)日：2023-04-18

申请号：US17102258

申请日：2020-11-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Syu-Tang Liu ,  Huang-Hsien Chang ,  Tsung-Tang Tsai ,  Hung-Jung Tu

IPC: H01L49/02 ,  H01L21/02 ,  H01L23/522 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/285

Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

公开(公告)号：US11581123B2

公开(公告)日：2023-02-14

申请号：US16937498

申请日：2020-07-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Syu-Tang Liu ,  Huang-Hsien Chang ,  Yunghsun Chen

IPC: H01F27/28 ,  H01F27/24 ,  H01F27/32 ,  H01F27/40 ,  H05K3/30 ,  H05K3/46 ,  H01F41/04 ,  H05K1/18

Abstract: An inductor unit includes a conductive structure, a first magnetic element and an insulating layer. The conductive structure has a bottom conductive layer, a top conductive layer, and a first side conductive layer extending from the bottom conductive layer to the top conductive layer. The first magnetic element is disposed on the bottom conductive layer of the conductive structure. The insulating layer is disposed on the bottom conductive layer of the conductive structure, wherein the insulating layer covers and surrounds the first magnetic element. The circuit structure including the inductor unit and the methods for manufacturing the same are also provided.

公开(公告)号：US11107881B2

公开(公告)日：2021-08-31

申请号：US16395156

申请日：2019-04-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shao Hsuan Chuang ,  Huang-Hsien Chang ,  Min Lung Huang ,  Yu Cheng Chen ,  Syu-Tang Liu

IPC: H01L49/02

Abstract: The subject application relates to a semiconductor package device, which includes a first conductive layer; a semiconductor wall disposed on the first conductive layer; a first conductive wall disposed on the first conductive layer; and an insulation layer disposed on the first conductive layer and between the semiconductor wall and the first conductive wall.

公开(公告)号：US11886015B2

公开(公告)日：2024-01-30

申请号：US17684377

申请日：2022-03-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shao Hsuan Chuang ,  Huang-Hsien Chang

IPC: G02B6/36 ,  H01L21/3065 ,  G02B6/42

CPC classification number: G02B6/3636 ,  G02B6/3632 ,  G02B6/4243 ,  H01L21/30655 ,  G02B6/3608

Abstract: A recessed portion in a semiconductor substrate and a method of forming the same are provided. The method comprises: forming a mask on the semiconductor substrate; forming a protection layer on a top surface of the mask and on at least one sidewall of the mask, and on at least one surface of the semiconductor substrate exposed by the mask; performing a first etching process to remove the protection layer on the top surface of the mask and on a bottom surface of the semiconductor substrate exposed by the mask; and performing a second etching process to remove the remaining protection layer and to etch the semiconductor substrate to form the recessed portion. In this way, a recessed portion with relatively smooth and vertical sidewalls can be realized.

公开(公告)号：US11728282B2

公开(公告)日：2023-08-15

申请号：US16656331

申请日：2019-10-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Syu-Tang Liu ,  Min Lung Huang ,  Huang-Hsien Chang ,  Tsung-Tang Tsai ,  Ching-Ju Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3512

Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.

公开(公告)号：US11411073B2

公开(公告)日：2022-08-09

申请号：US16802465

申请日：2020-02-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shao Hsuan Chuang ,  Huang-Hsien Chang ,  Min Lung Huang

IPC: H01L23/64 ,  H01L49/02 ,  H01L21/48 ,  H01L29/94 ,  H01L27/108 ,  H01L23/31

Abstract: A semiconductor package device includes a first conductive wall, a second conductive wall, a first insulation wall, a dielectric layer, a first electrode, and a second electrode. The first insulation wall is disposed between the first and second conductive walls. The dielectric layer has a first portion covering a bottom surface of the first conductive wall, a bottom surface of the second conductive wall and a bottom surface of the first insulation wall. The first electrode is electrically connected to the first conductive wall. The second electrode is electrically connected to the second conductive wall.

公开(公告)号：US11289411B2

公开(公告)日：2022-03-29

申请号：US16942579

申请日：2020-07-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Syu-Tang Liu ,  Tsung-Tang Tsai ,  Huang-Hsien Chang ,  Ching-Ju Chen

IPC: H05K1/02 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.

公开(公告)号：US10796987B2

公开(公告)日：2020-10-06

申请号：US16182588

申请日：2018-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long Lu ,  Huang-Hsien Chang

IPC: H01L23/12 ,  H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor packaging device includes a first patterned insulation layer, a patterned conductive layer, a semiconductor device and an encapsulant. The first patterned insulation layer has a first surface, a second surface opposite the first surface, and an island portion having the first surface. The first patterned insulation layer defines a tapered groove surrounding the island portion. The patterned conductive layer is disposed on the first surface of the island portion. The semiconductor device electrically connects to the patterned conductive layer. The encapsulant encapsulates the semiconductor device, the first patterned insulation layer and the patterned conductive layer.