公开(公告)号：US20240170396A1

公开(公告)日：2024-05-23

申请号：US18427796

申请日：2024-01-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Sheng-Wen YANG ,  Teck-Chong LEE ,  Yen-Liang HUANG

IPC: H01L23/522 ,  H01L23/12 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L23/12 ,  H01L23/31

Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.

公开(公告)号：US20240215151A1

公开(公告)日：2024-06-27

申请号：US18086579

申请日：2022-12-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Chiang SHIH ,  Cheng-Yuan KUNG ,  Hung-Yi LIN ,  Meng-Wei HSIEH ,  Chien-Mei HUANG ,  I-Ting LIN ,  Sheng-Wen YANG

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H05K1/0298 ,  H05K1/115 ,  H05K2201/09827

Abstract: The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a first redistribution structure and a first encapsulant. The first encapsulant supports the first redistribution structure and is configured to function as a first reinforcement to provide a second redistribution structure. The redistribution structure has a plurality of conductive layers disposed over the first redistribution structure.

公开(公告)号：US20220230946A1

公开(公告)日：2022-07-21

申请号：US17151062

申请日：2021-01-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Wei SHIH ,  Sheng-Wen YANG ,  Chung-Hung LAI ,  Chin-Li KAO

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31

Abstract: A substrate structure and a semiconductor package structure are provided. The substrate structure includes a first dielectric layer, a pad and a conductive structure. The first dielectric layer has a first surface and a second surface opposite to the first surface. The pad is adjacent to the first surface and at least partially embedded in the first dielectric layer. The first dielectric layer has an opening exposing the pad, and a width of the opening is less than a width of the pad. The conductive structure is disposed on the pad and composed of a first portion outside the opening of the first dielectric layer and a second portion embedded in the opening of the first dielectric layer. The first portion has an aspect ratio exceeding 1.375.

公开(公告)号：US20230197600A1

公开(公告)日：2023-06-22

申请号：US17555227

申请日：2021-12-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Sheng-Wen YANG ,  Teck-Chong LEE ,  Yen-Liang HUANG

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/12

CPC classification number: H01L23/5226 ,  H01L23/31 ,  H01L23/12

Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.

公开(公告)号：US20210151398A1

公开(公告)日：2021-05-20

申请号：US16684353

申请日：2019-11-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Teck-Chong LEE ,  Sheng-Wen YANG

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor device package includes a first semiconductor device; a second semiconductor device; and a first redistribution layer disposed on the first semiconductor device and having a side wall defining an opening that exposes the first semiconductor device. The side wall of the first redistribution layer has an average surface roughness (Ra) in a range up to 2 micrometers (μm).