公开(公告)号：US08889488B2

公开(公告)日：2014-11-18

申请号：US14016850

申请日：2013-09-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shin-Hua Chao ,  Chao-Yuan Liu ,  Hui-Ying Hsieh ,  Chih-Ming Chung

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/14 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L24/96 ,  H01L21/56 ,  H01L23/145 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括衬底，半导体元件，封装体和导电部件。 基板具有电接触。 半导体元件设置在基板上。 封装体覆盖半导体元件并且限定了电触头暴露的通孔。 其中，包装体包括树脂体和多个纤维层。 纤维层设置在树脂体中并限定多个布置成阵列的纤维孔。 导电部件通过通孔与基板电连接。

公开(公告)号：US10141252B2

公开(公告)日：2018-11-27

申请号：US15435143

申请日：2017-02-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Fu Sung ,  Shin-Hua Chao ,  Ming-Chi Liu ,  Hung-Sheng Chen

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes: a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole being further defined by a first sidewall and a second sidewall of the passivation layer; a first conductive layer on the first surface of the passivation layer and the first sidewall; a second conductive layer on the second surface of the passivation layer and the second sidewall; and a third conductive layer between the first conductive layer and the second conductive layer.