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    Semiconductor processing method of fabricating field effect transistors
    1.
    发明授权
    Semiconductor processing method of fabricating field effect transistors 失效
    制造场效应晶体管的半导体处理方法

    公开(公告)号：US06326250B1

    公开(公告)日：2001-12-04

    申请号：US08990200

    申请日：1997-12-22

    申请人： Aftab Ahmad ,  Kirk Prall

    发明人： Aftab Ahmad ,  Kirk Prall

    IPC分类号： H01L21336

    CPC分类号： H01L29/6653 ,  H01L21/823814

    摘要： In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second transistor gate. In another aspect, a semiconductor processing method includes: a) providing a semiconductor substrate; b) providing a transistor gate over the semiconductor substrate; c) providing spacers adjacent the transistor gate; d) providing electrically conductive source and drain implant regions within the substrate operatively adjacent the transistor gate; e) implanting a conductivity enhancing dopant into the previously formed electrically conductive source and drain regions; and f) driving the conductivity enhancing dopant under the spacers to form graded junction regions.

    摘要翻译： 在本发明的一个方面，半导体处理方法包括：a）提供半导体衬底; b）限定半导体衬底的第一导电类型区域和第二导电类型区域; c）在所述第一类型区域上提供限定与其可操作地相邻的第一源区域和第一漏极区域的第一晶体管栅极; d）在所述第二类型区域上提供限定与其可操作地相邻的第二源极区域和第二漏极区域的第二晶体管栅极; 以及e）通过所述第一导电区域的所述第一源极和漏极区域以及所述第二导电区域的所述第二源极和漏极区域覆盖所述第二导电类型的电导率增强掺杂剂，以在所述衬底内提供第二导电类型的常规LDD注入区域 可操作地与第一晶体管栅极相邻并且在衬底内提供可操作地邻近第二晶体管栅极的第二导电类型的晕圈注入区域。 另一方面，半导体处理方法包括：a）提供半导体衬底; b）在半导体衬底上提供晶体管栅极; c）提供与晶体管栅极相邻的间隔物; d）在所述衬底内提供与所述晶体管栅极可操作地相邻的导电源极和漏极注入区域; e）将电导率增强掺杂剂注入到先前形成的导电源极和漏极区域中; 以及f）在所述间隔物下驱动所述导电性增强掺杂剂以形成渐变连接区域。

    Semiconductor processing method of fabricating field effect transistors
    3.
    发明授权
    Semiconductor processing method of fabricating field effect transistors 失效

    公开(公告)号：US5849615A

    公开(公告)日：1998-12-15

    申请号：US604904

    申请日：1996-02-22

    申请人： Aftab Ahmad ,  Kirk Prall

    发明人： Aftab Ahmad ,  Kirk Prall

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/6653 ,  H01L21/823814

    摘要： In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second transistor gate. In another aspect, a semiconductor processing method includes: a) providing a semiconductor substrate; b) providing a transistor gate over the semiconductor substrate; c) providing spacers adjacent the transistor gate; d) providing electrically conductive source and drain implant regions within the substrate operatively adjacent the transistor gate; e) implanting a conductivity enhancing dopant into the previously formed electrically conductive source and drain regions; and f) driving the conductivity enhancing dopant under the spacers to form graded junction regions.

    High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS
    4.
    发明授权
    High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS 失效
    采用分裂多晶硅CMOS工艺的高性能PMOSFET，包含用于制造多兆位DRAMS的先进的堆叠电容单元

    公开(公告)号：US5716862A

    公开(公告)日：1998-02-10

    申请号：US491179

    申请日：1995-06-16

    申请人： Aftab Ahmad ,  Randhir P. S. Thakur ,  Kirk Prall ,  Tyler Lowrey ,  Brett Rolfson

    发明人： Aftab Ahmad ,  Randhir P. S. Thakur ,  Kirk Prall ,  Tyler Lowrey ,  Brett Rolfson

    IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/02 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L21/28061 ,  H01L21/28247

    摘要： This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. In one embodiment of the present invention teaches a semiconductor manufacturing process for forming p-channel devices by the steps of: defining p-channel transistor gate electrodes having substantially vertical sidewalls over n-well regions; performing a p-type impurity implant into the n-well regions to form p-channel source and drain terminals on opposing sides of each the p-channel transistor gate electrodes; performing an angled n-type impurity implant into the n-well regions to form an n-type halo around the p-channel source and drain terminals; performing a low temperature oxidation step at a temperature ranging between 600.degree.-957.degree. C., to form poly gate sidewall oxidation about the vertical sidewalls of the p-channel transistor gate electrodes; and performing a p-type impurity implant into the n-well regions.

    摘要翻译： 本发明是使用分裂多晶硅CMOS制造流程中的堆叠容器电容器单元制造动态随机存取存储器的方法。 分离多晶硅流程表示使用单独的掩蔽步骤由单个导电层（通常为掺杂多晶硅层）形成N沟道和P沟道晶体管栅极。 在本发明的一个实施例中，教导了通过以下步骤形成p沟道器件的半导体制造工艺：定义在n-阱区上具有基本上垂直的侧壁的p沟道晶体管栅电极; 对n阱区域进行p型杂质注入，以在每个p沟道晶体管栅电极的相对侧上形成p沟道源极和漏极端子; 在n阱区域中执行倾斜的n型杂质注入以在p沟道源极和漏极端子周围形成n型光晕; 在600〜957℃的温度范围内进行低温氧化步骤，以形成围绕p沟道晶体管栅极垂直侧壁的多晶硅侧壁氧化; 以及对n阱区进行p型杂质注入。

    Semiconductor processing method of fabricating field effect transistors
    5.
    发明授权
    Semiconductor processing method of fabricating field effect transistors 有权
    制造场效应晶体管的半导体处理方法

    公开(公告)号：US6150204A

    公开(公告)日：2000-11-21

    申请号：US192958

    申请日：1998-11-16

    申请人： Aftab Ahmad ,  Kirk Prall

    发明人： Aftab Ahmad ,  Kirk Prall

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/6653 ,  H01L21/823814

    摘要： In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second transistor gate. In another aspect, a semiconductor processing method includes: a) providing a semiconductor substrate; b) providing a transistor gate over the semiconductor substrate; c) providing spacers adjacent the transistor gate; d) providing electrically conductive source and drain implant regions within the substrate operatively adjacent the transistor gate; e) implanting a conductivity enhancing dopant into the previously formed electrically conductive source and drain regions; and f) driving the conductivity enhancing dopant under the spacers to form graded junction regions.

    摘要翻译： 在本发明的一个方面，半导体处理方法包括：a）提供半导体衬底; b）限定半导体衬底的第一导电类型区域和第二导电类型区域; c）在所述第一类型区域上提供限定与其可操作地相邻的第一源区域和第一漏极区域的第一晶体管栅极; d）在所述第二类型区域上提供限定与其可操作地相邻的第二源极区域和第二漏极区域的第二晶体管栅极; 以及e）通过所述第一导电区域的所述第一源极和漏极区域以及所述第二导电区域的所述第二源极和漏极区域覆盖所述第二导电类型的电导率增强掺杂剂，以在所述衬底内提供第二导电类型的常规LDD注入区域 可操作地与第一晶体管栅极相邻并且在衬底内提供可操作地邻近第二晶体管栅极的第二导电类型的晕圈注入区域。 另一方面，半导体处理方法包括：a）提供半导体衬底; b）在半导体衬底上提供晶体管栅极; c）提供与晶体管栅极相邻的间隔物; d）在所述衬底内提供与所述晶体管栅极可操作地相邻的导电源极和漏极注入区域; e）将电导率增强掺杂剂注入到先前形成的导电源极和漏极区域中; 以及f）在所述间隔物下驱动所述导电性增强掺杂剂以形成渐变连接区域。

    Method of forming a resistor and integrated circuitry having a resistor construction
    6.
    发明授权
    Method of forming a resistor and integrated circuitry having a resistor construction 有权
    形成电阻器的方法和具有电阻器结构的集成电路

    公开(公告)号：US06130137A

    公开(公告)日：2000-10-10

    申请号：US170792

    申请日：1998-10-13

    申请人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    发明人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    IPC分类号： H01L21/02 ,  H01L21/20

    CPC分类号： H01L28/20

    摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

    摘要翻译： 从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。 结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。 或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

    Method of forming a resistor and integrated circuitry having a resistor construction
    10.
    发明授权
    Method of forming a resistor and integrated circuitry having a resistor construction 失效
    形成电阻器的方法和具有电阻器结构的集成电路

    公开(公告)号：US5668037A

    公开(公告)日：1997-09-16

    申请号：US679705

    申请日：1996-07-11

    申请人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    发明人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L27/08 ,  H01L21/70

    CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802 ,  Y10S148/136

    摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

    摘要翻译： 从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。 结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。 或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。