公开(公告)号：US07406670B1

公开(公告)日：2008-07-29

申请号：US11888774

申请日：2007-08-01

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

IPC: G06F17/50 ,  G06F9/45 ,  H03K19/00

CPC classification number: G06F11/27

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.

Abstract translation: 用于生成具有嵌入式处理器的集成电路的测试程序的方法和装置。 一个实施例具有包括嵌入式微处理器的系统; 存储在存储器中的多个汇编语言指令，其中所述汇编语言指令基本上行使关键路径或最接近所述嵌入式微处理器中的关键路径的路径; 以及具有可编程时钟电路的可编程测试电路，用于向嵌入式微处理器提供倍增时钟信号，以执行汇编语言指令。

公开(公告)号：US06522167B1

公开(公告)日：2003-02-18

申请号：US09757760

申请日：2001-01-09

Applicant: Ahmad R. Ansari ,  Stephen M. Douglass ,  Mehul R. Vashi ,  Steven P. Young

Inventor： Ahmad R. Ansari ,  Stephen M. Douglass ,  Mehul R. Vashi ,  Steven P. Young

IPC: G06F738

CPC classification number: G06F15/7867

Abstract: A data processing system having a user configurable memory controller, one or more block RAMS, and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

Abstract translation: 具有用户可配置存储器控制器，一个或多个块RAMS和处理器核的数据处理系统可以被配置在单个现场可编程门阵列（FPGA）中。 块RAM的地址深度和等待状态的数量可以由用户选择，并且可以在FPGA的配置之前设置，也可以使用处理器核心的指令进行编程。 还公开了可以优化地址深度和等待状态数以达到性能水平的算法。 本发明可以应用于具有单独的指令和数据侧的设计。

公开(公告)号：US07269805B1

公开(公告)日：2007-09-11

申请号：US10836995

申请日：2004-04-30

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F11/27

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.

Abstract translation: 用于生成具有嵌入式处理器的集成电路的测试程序的方法和装置。 一个实施例具有包括嵌入式微处理器的系统; 存储在存储器中的多个汇编语言指令，其中所述汇编语言指令基本上行使关键路径或最接近所述嵌入式微处理器中的关键路径的路径; 以及具有可编程时钟电路的可编程测试电路，用于向嵌入式微处理器提供倍增时钟信号，以执行汇编语言指令。

公开(公告)号：US07624209B1

公开(公告)日：2009-11-24

申请号：US10941240

申请日：2004-09-15

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi ,  Alex Scott Warshofsky

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi ,  Alex Scott Warshofsky

IPC: G06F5/06 ,  G06F13/00

CPC classification number: G06F13/4273

Abstract: A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises steps of providing an address for a data transfer between a memory controller and a peripheral device; coupling an address valid signal to the peripheral device; transferring the data between the memory controller and the peripheral device; and receiving a data transfer complete signal at the memory controller. According to another aspect of the invention, an integrated circuit enabling a variable latency data transfer is described. The integrated circuit comprises peripheral device; a memory controller coupled to the peripheral device; an address valid signal coupled from the memory controller to the peripheral device; and a transfer complete signal coupled from the peripheral device to the memory controller.

Abstract translation: 描述了在诸如具有嵌入式处理器的FPGA的电子设备中实现可变延迟数据传输的方法。 根据本发明的一个方面，一种方法包括以下步骤：为存储器控制器和外围设备之间的数据传送提供地址; 将地址有效信号耦合到外围设备; 在存储器控制器和外围设备之间传送数据; 并在存储器控制器处接收数据传送完成信号。 根据本发明的另一方面，描述了实现可变等待时间数据传输的集成电路。 集成电路包括外围设备; 耦合到所述外围设备的存储器控​​制器; 从所述存储器控制器耦合到所述外围设备的地址有效信号; 以及从外围设备耦合到存储器控制器的传送完成信号。

公开(公告)号：US07007121B1

公开(公告)日：2006-02-28

申请号：US10084569

申请日：2002-02-27

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi

IPC: G06F13/362 ,  G06F1/08 ,  G06F5/06

CPC classification number: G06F13/4273 ,  G06F13/364

Abstract: A bus arbiter controls the bus frequency in a system that includes a plurality of bus masters and a plurality of slaves. The bus frequency is determined according to the internal frequency of the devices that are part of the transaction. Additionally, the bus frequency is set according to the length of the bus between the devices that are a part of the transaction and, correspondingly, the expected amount of impedance there between. As a part of the present invention, a master seeking bus resources to initiate a transaction generates a bus request and a destination address to the bus arbiter so that it may determine a corresponding bus frequency in advance. Thereafter, the bus arbiter sets the bus frequency to a value that corresponds to the transaction that is about to take place thereon. Next, the bus arbiter issues a grant signal to enable the master to use the bus. Each slave device for a transaction then generates or receives sample cycle signals indicating when a signal should be read on the bus.

Abstract translation: 总线仲裁器控制包括多个总线主机和多个从机的系统中的总线频率。 总线频率根据作为交易一部分的设备的内部频率确定。 此外，总线频率根据总线在作为交易的一部分的设备之间的长度设置，相应地，其间的预期阻抗量设置。 作为本发明的一部分，寻求总线资源以启动事务的主机向总线仲裁器生成总线请求和目的地地址，使得它可以预先确定相应的总线频率。 此后，总线仲裁器将总线频率设置为与要在其上进行的事务相对应的值。 接下来，总线仲裁器发出授权信号，以使主机能够使用总线。 每个用于交易的从设备都生成或接收采样周期信号，指示何时应在总线上读取信号。

公开(公告)号：US08006021B1

公开(公告)日：2011-08-23

申请号：US12057326

申请日：2008-03-27

Applicant: Kam-Wing Li ,  Jeffery H. Appelbaum ,  Ahmad R. Ansari

Inventor： Kam-Wing Li ,  Jeffery H. Appelbaum ,  Ahmad R. Ansari

IPC: G06F13/36

CPC classification number: G06F13/4059

Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Abstract translation: 描述了一种用于嵌入IC的处理器块ASIC核心的处理器局部总线桥。 核心逻辑到核心逻辑桥包括从处理器本地总线接口，耦合到从属处理器本地总线接口的交叉开关和耦合到交叉开关的主处理器本地总线接口。 从处理器本地总线接口和主处理器本地总线接口通过交叉开关彼此耦合，用于核心逻辑的第一和第二部分之间的双向通信。 桥接器提供用于桥接的速率适配，以使用与交叉开关相关联的操作频率，其具有比与主处理器和从属处理器局部总线接口的核心逻辑侧相关联的操作频率更大的操作频率。

公开(公告)号：US07737725B1

公开(公告)日：2010-06-15

申请号：US12098400

申请日：2008-04-04

Applicant: Ahmad R. Ansari ,  Kam-Wing Li

Inventor： Ahmad R. Ansari ,  Kam-Wing Li

IPC: G06F7/38 ,  H03K19/173

CPC classification number: G06F15/7867

Abstract: A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

Abstract translation: 描述了用于处理器块的设备控制寄存器控制器专用集成电路（“ASIC”）核心。 器件控制寄存器从器件块耦合到器件控制寄存器控制器，并且可以访问处理器块ASIC核心的多个接口的器件寄存器。 主设备接口用于将处理器块ASIC核心外部的至少一个从设备耦合到设备控制寄存器控制器。 从设备接口用于将处理器块ASIC核心外部的主设备耦合到设备控制寄存器控制器。

公开(公告)号：US07673087B1

公开(公告)日：2010-03-02

申请号：US12057322

申请日：2008-03-27

Applicant: Ahmad R. Ansari ,  Jeffery H. Applebaum ,  Kunal R. Shenoy

Inventor： Ahmad R. Ansari ,  Jeffery H. Applebaum ,  Kunal R. Shenoy

IPC: G06F13/14

CPC classification number: G06F13/366 ,  Y10S370/911

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract translation: 描述了处理器块核心的仲裁。 主设备与嵌入在主机集成电路（“IC”）中的处理器块核心相关联。 主设备通过作为处理器块核心的一部分的交叉开关和桥接器耦合到主机IC的核心逻辑。 交叉开关包括仲裁器。 仲裁协议是从仲裁器中使用的仲裁协议中选出的。 被审查的待处理事务被轮询以使用所选择的仲裁协议访问该桥以进行仲裁。

公开(公告)号：US07200723B1

公开(公告)日：2007-04-03

申请号：US10913282

申请日：2004-08-06

Applicant: Ahmad R. Ansari ,  Kathryn Story Purcell

Inventor： Ahmad R. Ansari ,  Kathryn Story Purcell

IPC: G06F12/00

CPC classification number: G06F12/063 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/355 ,  G06F9/3822 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3897

Abstract: An interface for accessing a bank of registers is described. A controller is coupled to receive address information, read information and write information. The device control register interface includes: a data bus for receiving data, pointer information and operation delineation information; a decoder coupled to receive the read information, the write information, the pointer information and the operation delineation information, where the decoder is configured to provide activation signaling responsive to information received; and the bank of registers coupled to the decoder to receive the activation signaling and coupled to the data bus for receiving the data, where the address information is for the bank or registers and where a single address is used for accessing all registers in the bank of registers.

Abstract translation: 描述用于访问一组寄存器的接口。 控制器被耦合以接收地址信息，读取信息和写入信息。 设备控制寄存器接口包括：用于接收数据的数据总线，指针信息和操作描画信息; 耦合以接收读取信息，写入信息，指针信息和操作描绘信息的解码器，其中解码器被配置为响应于所接收的信息提供激活信令; 以及耦合到解码器的寄存器组，以接收激活信令并耦合到数据总线以接收数据，其中地址信息用于存储体或寄存器，并且其中单个地址用于访问存储体中的所有寄存器 注册

公开(公告)号：US06886092B1

公开(公告)日：2005-04-26

申请号：US10001871

申请日：2001-11-19

Applicant: Stephen M. Douglass ,  Ahmad R. Ansari

Inventor： Stephen M. Douglass ,  Ahmad R. Ansari

IPC: G06F9/38 ,  G06F9/44 ,  G06F15/00 ,  G06F15/78

CPC classification number: G06F15/7867 ,  G06F9/3877 ,  G06F9/3897

Abstract: A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code. The processing continues when the fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.

Abstract translation: 当可编程门阵列中嵌入的固定逻辑处理器检测到定制操作代码时，开始用于处理可编程门阵列内的数据的方法和装置。 当固定逻辑处理器向可编程门阵列提供自定义操作码的指示时，该处理继续。 该处理通过将可配置为专用处理器的可编程门阵列的至少一部分在从固定逻辑处理器接收到指示时执行固定逻辑例程而继续进行。