公开(公告)号：US07730244B1

公开(公告)日：2010-06-01

申请号：US12057314

申请日：2008-03-27

Applicant: Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray

Inventor： Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray

IPC: G06F13/00

CPC classification number: G06F13/28 ,  G06F13/385

Abstract: Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.

Abstract translation: 描述突发命令的命令转换。 一个从属处理器本地总线（“PLB”）桥接器，嵌入在主机IC中的处理器块核心的一部分，具有允许访问交叉开关器件的数据大小阈值。 耦合到从属PLB桥的主设备具有多个命令总线宽度中的任何一个。 经由命令总线发出突发命令，该命令总线具有来自主PLB桥的主设备的多个命令总线宽度。 如果命令总线宽度不等于本地总线宽度，则突发命令将转换为从属处理器逻辑块的本机总线宽度。 如果突发命令的执行将超过数据大小阈值并且如果突发命令的执行不会超过数据大小阈值，则转换而不进行转换，则转换突发命令。

公开(公告)号：US08006021B1

公开(公告)日：2011-08-23

申请号：US12057326

申请日：2008-03-27

Applicant: Kam-Wing Li ,  Jeffery H. Appelbaum ,  Ahmad R. Ansari

Inventor： Kam-Wing Li ,  Jeffery H. Appelbaum ,  Ahmad R. Ansari

IPC: G06F13/36

CPC classification number: G06F13/4059

Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Abstract translation: 描述了一种用于嵌入IC的处理器块ASIC核心的处理器局部总线桥。 核心逻辑到核心逻辑桥包括从处理器本地总线接口，耦合到从属处理器本地总线接口的交叉开关和耦合到交叉开关的主处理器本地总线接口。 从处理器本地总线接口和主处理器本地总线接口通过交叉开关彼此耦合，用于核心逻辑的第一和第二部分之间的双向通信。 桥接器提供用于桥接的速率适配，以使用与交叉开关相关联的操作频率，其具有比与主处理器和从属处理器局部总线接口的核心逻辑侧相关联的操作频率更大的操作频率。

公开(公告)号：US07737725B1

公开(公告)日：2010-06-15

申请号：US12098400

申请日：2008-04-04

Applicant: Ahmad R. Ansari ,  Kam-Wing Li

Inventor： Ahmad R. Ansari ,  Kam-Wing Li

IPC: G06F7/38 ,  H03K19/173

CPC classification number: G06F15/7867

Abstract: A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

Abstract translation: 描述了用于处理器块的设备控制寄存器控制器专用集成电路（“ASIC”）核心。 器件控制寄存器从器件块耦合到器件控制寄存器控制器，并且可以访问处理器块ASIC核心的多个接口的器件寄存器。 主设备接口用于将处理器块ASIC核心外部的至少一个从设备耦合到设备控制寄存器控制器。 从设备接口用于将处理器块ASIC核心外部的主设备耦合到设备控制寄存器控制器。

公开(公告)号：US07970977B1

公开(公告)日：2011-06-28

申请号：US12363610

申请日：2009-01-30

Applicant: Kam-Wing Li ,  Ahmad R. Ansari ,  Sanford L. Helton ,  Tomai Knopp ,  Khang Kim Dao ,  Jeffrey H. Seltzer

Inventor： Kam-Wing Li ,  Ahmad R. Ansari ,  Sanford L. Helton ,  Tomai Knopp ,  Khang Kim Dao ,  Jeffrey H. Seltzer

IPC: G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F9/26

CPC classification number: G06F13/4036

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract translation: 桥接总线桥内的多个总线的方法可以包括确定总线桥的队列是否包括指向受限地址范围的事务请求，并且对于每个接收的事务请求，确定事务请求的地址是否为 指示在受限地址范围内。 可以根据交易请求所针对的地址是否在受限地址范围内以及该队列是否包括指向受限地址范围的交易请求，来选择性地拒绝总线桥接器接收的每个交易请求。

公开(公告)号：US08248883B1

公开(公告)日：2012-08-21

申请号：US12873041

申请日：2010-08-31

Applicant: Ting Lu ,  Kam-Wing Li ,  Anatoly Belkin ,  Ahmad R. Ansari

Inventor： Ting Lu ,  Kam-Wing Li ,  Anatoly Belkin ,  Ahmad R. Ansari

IPC: G11C8/00

CPC classification number: G11C8/06 ,  G06F2213/0038

Abstract: A system for implementing a non-volatile input/output (I/O) device based memory can include an interface configured to receive a processor request specifying a data unit. The data unit can be specified by a processor address. The system can include an address-data converter coupled to the interface. The address-data converter can be configured to correlate the processor address of the data unit to a data block within the non-volatile I/O device. The system further can include an I/O controller coupled to the address-data converter. The I/O controller can be configured to issue a non-volatile I/O device command specifying the data block to the non-volatile I/O device.

Abstract translation: 用于实现基于非易失性输入/输出（I / O）设备的存储器的系统可以包括被配置为接收指定数据单元的处理器请求的接口。 数据单元可以由处理器地址指定。 该系统可以包括耦合到接口的地址数据转换器。 地址数据转换器可以被配置为将数据单元的处理器地址与非易失性I / O设备内的数据块相关联。 该系统还可以包括耦合到地址数据转换器的I / O控制器。 I / O控制器可配置为向非易失性I / O设备发出指定数据块的非易失性I / O设备命令。

公开(公告)号：US08185720B1

公开(公告)日：2012-05-22

申请号：US12043097

申请日：2008-03-05

Applicant: Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray ,  Kathryn S. Purcell ,  Alex S. Warshofsky

Inventor： Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray ,  Kathryn S. Purcell ,  Alex S. Warshofsky

IPC: G06F15/76

CPC classification number: G06F15/7889

Abstract: A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller. Additional or other interfaces may be coupled to the crossbar interconnect.

Abstract translation: 硬连线核心嵌入具有可编程电路的集成电路中。 硬接线芯具有微处理器; 耦合到微处理器的处理器本地总线的交叉开关互连; 以及耦合到交叉开关互连的存储器控​​制器接口。 交叉连接提供用于将硬连线核心耦合到可编程电路的管线。 微处理器，交叉开关互连和存储器控制器接口都能够以第一操作频率操作，并且存储器控制器接口还能够被设置为在第二操作频率下操作，其具有相对于 第一个操作频率。 交叉开关互连被配置为将由微处理器发起的事务定向到存储器控制器接口，用于经由存储器控制器访问耦合到存储器控制器接口的一个或多个存储器件。 附加或其他接口可以耦合到交叉开关互连。

公开(公告)号：US08161212B1

公开(公告)日：2012-04-17

申请号：US12888333

申请日：2010-09-22

Applicant: Ting Lu ,  Kam-Wing Li ,  Bradley L. Taylor

Inventor： Ting Lu ,  Kam-Wing Li ,  Bradley L. Taylor

IPC: G06F13/12 ,  G06F3/00 ,  G06F1/12

CPC classification number: G06F13/1684

Abstract: An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.

Abstract translation: 用于实现多个非易失性输入/输出（I / O）设备的并行使用的系统的实施例可以包括被配置为从源接收源请求和耦合到该接口的第一存储器的接口。 可以将第一个存储器配置为存储源请求指定的数据单元。 该系统可以包括耦合到该接口的I / O设备控制器。 I / O设备控制器可以被配置为将源请求与多个I / O设备请求相关联，并且并行发起多个I / O设备请求到多个非易失性I / O设备。 该系统还可以包括耦合到第一存储器和I / O设备控制器的解码器。 解码器可以被配置为并行地从多个非易失性I / O设备接收数据。

公开(公告)号：US07715443B1

公开(公告)日：2010-05-11

申请号：US10728657

申请日：2003-12-05

Applicant: Kam-Wing Li

Inventor： Kam-Wing Li

IPC: H04J3/07 ,  H04L25/00 ,  H04L7/00

CPC classification number: H04J3/0632 ,  H04J3/073 ,  Y10S370/907

Abstract: The techniques described herein allow a more efficient transmuxing operation for transferring data from a synchronous domain (e.g., SONET) to a plesiochronous (e.g., PDH) domain as compared to the prior art, in which extraction of data streams, jitter filtering and stuff bit generation are processed separately. The techniques described herein include extraction of data from the plesiochronous data stream without complete extraction of the underlying native data stream. Filtering is performed based on synchronous timing, which results in a simpler filter design.

Abstract translation: 与现有技术相比，本文描述的技术允许更有效的转换操作，用于将数据从同步域（例如，SONET）传送到同步（例如，PDH）域，其中提取数据流，抖动滤波和填充位 一代分开处理。 本文所描述的技术包括从同步数据流中提取数据，而不完全提取底层本机数据流。 基于同步定时进行滤波，从而实现更简单的滤波器设计。

公开(公告)号：US09483416B1

公开(公告)日：2016-11-01

申请号：US12909493

申请日：2010-10-21

Applicant: Ting Lu ,  Stephen M. Trimberger ,  Eric E. Edwards ,  Weiguang Lu ,  Kam-Wing Li

Inventor： Ting Lu ,  Stephen M. Trimberger ,  Eric E. Edwards ,  Weiguang Lu ,  Kam-Wing Li

IPC: G06F12/14 ,  G06F11/30

CPC classification number: G06F12/14 ,  G06F11/00 ,  G06F11/30 ,  G06F21/575

Abstract: A method of processor operation using an integrated circuit (IC) can include loading encrypted program code into the IC through a configuration port of the IC and decrypting the encrypted program code using configuration circuitry of the IC. Decryption of the encrypted program code can result in decrypted program code which can be provided to a target destination.

Abstract translation: 使用集成电路（IC）的处理器操作的方法可以包括通过IC的配置端口将加密的程序代码加载到IC中，并使用IC的配置电路解密加密的程序代码。 加密程序代码的解密可以产生可以提供给目标目的地的解密的程序代码。

公开(公告)号：US06578153B1

公开(公告)日：2003-06-10

申请号：US09527323

申请日：2000-03-16

Applicant: Wayne Robert Sankey ,  Kyl Scott ,  Osman Koyuncu ,  Kam-Wing Li ,  Ritesh Dhirajlal Sojitra

Inventor： Wayne Robert Sankey ,  Kyl Scott ,  Osman Koyuncu ,  Kam-Wing Li ,  Ritesh Dhirajlal Sojitra

IPC: H04L700

CPC classification number: H04L1/00

Abstract: In one aspect, the present invention provides a method of communicating across a serial line 26. In this method, n parallel streams of data 30 are to be received at a destination 20. In a first embodiment, the n parallel streams of data 30 characterized in that one of streams of data includes a unique characteristic that can be used to distinguish that one from each of the other streams of data. In a second embodiment, each of the n streams of data 30 are in a particular pattern that includes a detectable characteristic. At the destination 20, the unique characteristic and/or detectable characteristic can be detected to correct space and/or time errors in the streams of data. For example, the destination 20 might be a receiver that includes a serial-to-parallel converter 28 and calibration circuitry 34.

Abstract translation: 在一个方面，本发明提供了一种在串行线26上进行通信的方法。在该方法中，将在目的地20处接收n个并行数据流30。在第一实施例中，数据30的n个并行流的特征在于 数据流中的一个包括可以用于将其与每个其他数据流区分开的唯一特性。 在第二实施例中，n个数据流30中的每一个是包括可检测特性的特定模式。 在目的地20，可以检测独特的特征和/或可检测的特性以校正数据流中的空间和/或时间误差。 例如，目的地20可以是包括串行到并行转换器28和校准电路34的接收机。