公开(公告)号：US20100044761A1

公开(公告)日：2010-02-25

申请号：US12603353

申请日：2009-10-21

申请人： Akif SULTAN ,  James F. BULLER ,  Kaveri MATHUR

发明人： Akif SULTAN ,  James F. BULLER ,  Kaveri MATHUR

IPC分类号： H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/7843

摘要： A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.

摘要翻译： 提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层 地区。 有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。 栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。 每个栅电极指部分的一部分覆盖有源区。 圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。 压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

公开(公告)号：US20090057729A1

公开(公告)日：2009-03-05

申请号：US11846318

申请日：2007-08-28

申请人： Akif SULTAN ,  James F. BULLER ,  Kaveri MATHUR

发明人： Akif SULTAN ,  James F. BULLER ,  Kaveri MATHUR

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/7843

摘要： A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.

摘要翻译： 提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层 地区。 有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。 栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。 每个栅电极指部分的一部分覆盖有源区。 圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。 压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

公开(公告)号：US20090081860A1

公开(公告)日：2009-03-26

申请号：US11861534

申请日：2007-09-26

申请人： Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

发明人： Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

IPC分类号： H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083

摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

摘要翻译： 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。 创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

公开(公告)号：US20090081837A1

公开(公告)日：2009-03-26

申请号：US11861492

申请日：2007-09-26

申请人： Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

发明人： Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/78 ,  H01L29/7843

摘要： The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

摘要翻译： 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

公开(公告)号：US20110303980A1

公开(公告)日：2011-12-15

申请号：US12797420

申请日：2010-06-09

申请人： Akif SULTAN ,  Indradeep SEN

发明人： Akif SULTAN ,  Indradeep SEN

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L27/088 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/7848

摘要： Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.

摘要翻译： 提供了半导体器件结构和相关制造方法的装置。 在半导体材料的隔离区域上制造半导体器件结构的方法包括形成覆盖半导体材料的隔离区域和掩蔽半导体材料的隔离区域的边缘部分的多个栅极结构。 当边缘部分被掩蔽时，制造方法通过在多个栅极结构的栅极结构之间形成凹槽并在凹部中形成应力区域来继续。 该方法继续通过揭开边缘部分并将导电性确定杂质类型的离子注入到应力区域和边缘部分中。

公开(公告)号：US20110171801A1

公开(公告)日：2011-07-14

申请号：US12684697

申请日：2010-01-08

申请人： Akif SULTAN

发明人： Akif SULTAN

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/78

摘要： A method of fabricating p-type metal oxide semiconductor (PMOS) transistor devices on a common substrate is presented. The method provides a first portion of semiconductor material and a second portion of semiconductor material on the common substrate. The first portion of semiconductor material and the second portion of semiconductor material are insulated from each other. The method continues by creating first PMOS transistor devices using the first portion of semiconductor material. The first PMOS transistor devices include stressor regions that impart compressive stress to channel regions of the first PMOS transistor devices. The method also creates second PMOS transistor devices using the second portion of semiconductor material. The second PMOS transistor devices do not include channel stressor regions.

摘要翻译： 提出了在公共衬底上制造p型金属氧化物半导体（PMOS）晶体管器件的方法。 该方法提供半导体材料的第一部分和半导体材料的第二部分在公共基底上。 半导体材料的第一部分和半导体材料的第二部分彼此绝缘。 该方法通过使用半导体材料的第一部分创建第一PMOS晶体管器件来继续。 第一PMOS晶体管器件包括对第一PMOS晶体管器件的沟道区赋予压应力的应力源区域。 该方法还使用半导体材料的第二部分创建第二PMOS晶体管器件。 第二PMOS晶体管器件不包括沟道应力区域。

公开(公告)号：US20090078991A1

公开(公告)日：2009-03-26

申请号：US11861051

申请日：2007-09-25

申请人： Akif SULTAN ,  Mark MICHAEL ,  David WU ,  Donna Michael

发明人： Akif SULTAN ,  Mark MICHAEL ,  David WU ,  Donna Michael

IPC分类号： H01L29/78 ,  H01L21/762

CPC分类号： H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

摘要： A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

摘要翻译： 提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。 有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。 第二类应力层设置在活动区域​​的第二侧边缘附近。

公开(公告)号：US20130092957A1

公开(公告)日：2013-04-18

申请号：US13692369

申请日：2012-12-03

申请人： Indradeep SEN ,  Thorsten KAMMLER ,  Andreas KNORR ,  Akif SULTAN

发明人： Indradeep SEN ,  Thorsten KAMMLER ,  Andreas KNORR ,  Akif SULTAN

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

摘要： A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

摘要翻译： 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。