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    SELF-ALIGNED SILICIDATION FOR REPLACEMENT GATE PROCESS
    1.
    发明申请
    SELF-ALIGNED SILICIDATION FOR REPLACEMENT GATE PROCESS 有权
    用于替代浇注过程的自对准硅化物

    公开(公告)号：US20130092957A1

    公开(公告)日：2013-04-18

    申请号：US13692369

    申请日：2012-12-03

    申请人： Indradeep SEN ,  Thorsten KAMMLER ,  Andreas KNORR ,  Akif SULTAN

    发明人： Indradeep SEN ,  Thorsten KAMMLER ,  Andreas KNORR ,  Akif SULTAN

    IPC分类号： H01L29/78

    CPC分类号： H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

    摘要： A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

    摘要翻译： 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

    SEMICONDUCTOR STRUCTURES AND METHODS FOR STABILIZING SILICON-COMPRISING STRUCTURES ON A SILICON OXIDE LAYER OF A SEMICONDUCTOR SUBSTRATE
    5.
    发明申请
    SEMICONDUCTOR STRUCTURES AND METHODS FOR STABILIZING SILICON-COMPRISING STRUCTURES ON A SILICON OXIDE LAYER OF A SEMICONDUCTOR SUBSTRATE 审中-公开
    用于稳定半导体衬底的氧化硅层上的含硅结构的半导体结构和方法

    公开(公告)号：US20100308440A1

    公开(公告)日：2010-12-09

    申请号：US12480286

    申请日：2009-06-08

    申请人： Frank S. JOHNSON ,  Andreas KNORR

    发明人： Frank S. JOHNSON ,  Andreas KNORR

    IPC分类号： H01L21/302 ,  H01L29/06

    CPC分类号： H01L29/66795

    摘要： Methods are provided for substantially preventing and filling overetched regions in a silicon oxide layer of a semiconductor substrate. The overetched regions may be formed as a result of overetching of the silicon oxide layer during etching of an overlying silicon-comprising material layer to form a silicon-comprising structure. An etch resistant spacer may be formed after the initial or subsequent overetches. The etch resistant spacer may be formed by depositing an etch resistant material into the overetched region and etching the deposited etch resistant material to leave residual etch resistant material forming the etch resistant spacer. The etch resistant spacer may also be formed by exposing the silicon oxide layer in the overetched region to a nitrogen-supplying material to form a silicon oxynitride etch resistant spacer.

    摘要翻译： 提供了用于基本上防止和填充半导体衬底的氧化硅层中的过蚀刻区域的方法。 在蚀刻覆盖的含硅材料层以形成含硅结构的过程中，可以形成过蚀刻区域作为氧化硅层的过蚀刻的结果。 可以在初始或随后的过程之后形成耐蚀刻间隔物。 耐蚀刻间隔物可以通过将抗蚀刻材料沉积到过蚀刻区域中并蚀刻沉积的耐蚀刻材料以形成形成耐蚀刻间隔物的残留耐蚀刻材料来形成。 也可以通过将过蚀区域中的氧化硅层暴露于氮供给材料以形成氮氧化硅耐腐蚀间隔物来形成耐蚀刻间隔物。

    SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING ISOLATION BETWEEN FIN STRUCTURES OF FINFET DEVICES
    7.
    发明申请
    SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING ISOLATION BETWEEN FIN STRUCTURES OF FINFET DEVICES 有权
    半导体结构和在FINFET器件的FIN结构之间形成隔离的方法

    公开(公告)号：US20110068431A1

    公开(公告)日：2011-03-24

    申请号：US12562849

    申请日：2009-09-18

    申请人： Andreas KNORR ,  Frank Scott JOHNSON

    发明人： Andreas KNORR ,  Frank Scott JOHNSON

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

    摘要： Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HPDCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability.

    摘要翻译： 提供了用于形成由体硅晶片形成的翅片结构之间的隔离的半导体结构和方法。 提供具有由其形成的一个或多个翅片结构的体硅晶片。 翅片结构的形成限定了一个或多个翅片结构之间的隔离沟槽。 每个翅片结构都具有垂直侧壁。 使用HPDCVD以大约4:1的比例或更大的比例在隔离沟槽和垂直侧壁上沉积氧化物层。 氧化层被各向同性蚀刻以从隔离沟底部的垂直侧壁和氧化物层的一部分去除氧化物层。 在隔离沟槽的底部上形成基本上均匀的厚的隔离氧化物层，以隔离一个或多个翅片结构，并显着降低翅片高度的可变性。

    METHODS FOR FABRICATING BULK FINFET DEVICES HAVING DEEP TRENCH ISOLATION
    8.
    发明申请
    METHODS FOR FABRICATING BULK FINFET DEVICES HAVING DEEP TRENCH ISOLATION 有权
    用于制造具有深度分离隔离的块状FINFET器件的方法

    公开(公告)号：US20110045648A1

    公开(公告)日：2011-02-24

    申请号：US12544931

    申请日：2009-08-20

    申请人： Andreas KNORR ,  Frank Scott JOHNSON

    发明人： Andreas KNORR ,  Frank Scott JOHNSON

    IPC分类号： H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/76232 ,  H01L29/66795 ,  H01L29/7851

    摘要： Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon.

    摘要翻译： 提供了用于制造具有深沟槽隔离的块状FinFET器件的方法。 在体硅晶片中形成一个或多个深隔离沟槽。 在其上的沉积硅晶片和介质垫层上沉积形成心轴的材料，同时沉积到作为填充材料的沟槽中。 形成心轴，其过蚀刻在沟槽上端形成凹部。 制造侧壁间隔件的共形侧壁间隔材料沉积在芯轴上并且形成凹槽，形成覆盖沟槽中的填充材料的间隔物。 使用间隔物去除心轴作为蚀刻停止。 使用侧壁间隔物作为蚀刻掩模，从体硅晶片形成翅片结构。 心轴形成材料是非晶和/或多晶硅。

    SEMICONDUCTOR STRUCTURES AND METHODS FOR REDUCING SILICON OXIDE UNDERCUTS IN A SEMICONDUCTOR SUBSTRATE
    10.
    发明申请
    SEMICONDUCTOR STRUCTURES AND METHODS FOR REDUCING SILICON OXIDE UNDERCUTS IN A SEMICONDUCTOR SUBSTRATE 审中-公开
    用于减少半导体衬底中的氧化硅衬底的半导体结构和方法

    公开(公告)号：US20100308382A1

    公开(公告)日：2010-12-09

    申请号：US12480279

    申请日：2009-06-08

    申请人： Frank S. JOHNSON ,  Andreas KNORR

    发明人： Frank S. JOHNSON ,  Andreas KNORR

    IPC分类号： H01L29/78 ,  H01L21/302 ,  H01L21/28

    CPC分类号： H01L29/66795 ,  H01L21/3065

    摘要： Methods are provided for fabricating semiconductor structures with an etch resistant layer that reduces undercuts in a silicon oxide layer of a semiconductor substrate. The semiconductor substrate is provided having the silicon oxide layer. The etch resistant layer is formed which uses at least a portion of the silicon oxide layer. A silicon-comprising material layer is formed overlying the etch resistant layer. The silicon-comprising material layer has an etch rate greater than an etch rate of the etch resistant layer when subjected to an etchant. The silicon-comprising material layer is etched with an etchant to form a fin structure on the silicon oxide layer. The etch resistant layer may be formed by ion implantation, diffusing nitrogen-supplying species into the silicon oxide layer, or forming an insulator material layer overlying the silicon oxide layer.

    摘要翻译： 提供了用于制造具有减少半导体衬底的氧化硅层中的底切的耐蚀刻层的半导体结构的方法。 提供具有氧化硅层的半导体衬底。 形成耐蚀层，其使用氧化硅层的至少一部分。 形成覆盖耐蚀刻层的含硅材料层。 当经受蚀刻剂时，含硅材料层的蚀刻速率大于耐蚀刻层的蚀刻速率。 用蚀刻剂蚀刻含硅材料层，以在氧化硅层上形成翅片结构。 耐蚀刻层可以通过离子注入形成，将氮供应物质扩散到氧化硅层中，或者形成覆盖氧化硅层的绝缘体材料层。