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    Registration accuracy measurement mark
    3.
    发明授权
    Registration accuracy measurement mark 失效
    注册精度测量标记

    公开(公告)号：US5892291A

    公开(公告)日：1999-04-06

    申请号：US670313

    申请日：1996-06-27

    申请人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

    发明人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

    IPC分类号： G03F1/36 ,  G03F1/42 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027 ,  H05K1/02 ,  H01L23/544

    CPC分类号： G03F7/706 ,  G03F7/70633 ,  Y10T428/24802 ,  Y10T428/24917

    摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

    摘要翻译： 本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件， 以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。 第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案 。 因此，可以提供考虑到像差影响的配准精度测量标记。

    Manufacturing method and manufacturing system of semiconductor device
    6.
    发明授权
    Manufacturing method and manufacturing system of semiconductor device 有权
    半导体器件的制造方法和制造系统

    公开(公告)号：US08043772B2

    公开(公告)日：2011-10-25

    申请号：US12466695

    申请日：2009-05-15

    申请人： Toshiharu Miwa ,  Junko Konishi ,  Toshihide Kawachi ,  Shigenori Yamashita ,  Takeshi Tashiro ,  Hidekimi Fudo

    发明人： Toshiharu Miwa ,  Junko Konishi ,  Toshihide Kawachi ,  Shigenori Yamashita ,  Takeshi Tashiro ,  Hidekimi Fudo

    IPC分类号： G03F9/00

    CPC分类号： G03F7/70641 ,  G03F7/70625

    摘要： In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.

    摘要翻译： 在形成晶片上的半导体器件的预定电路图形的曝光工艺中，测量在过去时刻在曝光处理中形成在晶片上的抗蚀剂图案的抗蚀剂尺寸和聚焦位置。 通过使用被测量的抗蚀剂尺寸和聚焦位置的测量结果来估计第二次进行曝光处理的晶片的抗蚀剂尺寸和聚焦位置，并且通过使用估计的抗蚀剂尺寸的估计值来计算聚焦偏移值， 焦点位置。 然后，考虑该聚焦偏移值计算曝光剂量，并且通过使用计算出的曝光剂量和聚焦偏移值，在进行了曝光处理的晶片上形成抗蚀剂图案。

    Photomask, semiconductor device, and method for exposing through photomask
    7.
    发明授权
    Photomask, semiconductor device, and method for exposing through photomask 失效
    光掩模，半导体器件和通过光掩模曝光的方法

    公开(公告)号：US06617080B1

    公开(公告)日：2003-09-09

    申请号：US09563953

    申请日：2000-05-02

    申请人： Toshihide Kawachi ,  Takuya Matsushita ,  Shigenori Yamashita ,  Yuki Miyamoto ,  Atsushi Ueno ,  Shinroku Maejima

    发明人： Toshihide Kawachi ,  Takuya Matsushita ,  Shigenori Yamashita ,  Yuki Miyamoto ,  Atsushi Ueno ,  Shinroku Maejima

    IPC分类号： G03F900

    CPC分类号： G03F7/70633

    摘要： The present invention provides a photomask, a semiconductor device, and a method for exposing through the photomask. The photomask comprises a photomask substrate, and an on-mask circuit area including an on-mask circuit pattern and an on-mask test mark area including an on-mask test pattern, both formed on the surface of the substrate, wherein the photomask substrate further includes an on-mask photolithography screening mark area including an on-mask comparison pattern and an on-mask screening pattern, the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern. The present invention allows it to measure the actual displacement generated from an overlaying (i.e. alignment) process for the purpose of eliminating of an the overlay displacement which can take place in a photolithography process.

    摘要翻译： 本发明提供了一种光掩模，半导体器件和用于曝光光掩模的方法。 光掩模包括光掩模基板和包括掩模电路图案的掩模电路区域和包括掩模测试图案的掩模测试标记区域，二者都形成在基板的表面上，其中光掩模基板 进一步包括包括掩膜比较图案和掩模屏蔽图案的掩模光刻掩模标记区域，掩模比较图案具有与至少一部分屏蔽电路图案基本相同的配置，以及 掩模掩模图案具有与掩模测试图案的至少一部分基本相同的构造。 本发明允许它测量从重叠（即对准）过程产生的实际位移，以消除可能在光刻工艺中发生的覆盖位移。