公开(公告)号：US06822279B2

公开(公告)日：2004-11-23

申请号：US10077767

申请日：2002-02-20

申请人： Shinya Soeda

发明人： Shinya Soeda

IPC分类号： H01L27108

CPC分类号： H01L23/552 ,  H01L23/5225 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate and a resistor group and/or a signal interconnection layer in a region of the semiconductor substrate. A shielding layer is located above and/or below the region where the resistor group and/or the signal interconnection layer are located.

摘要翻译： 半导体器件在半导体衬底的区域中具有半导体衬底和电阻器组和/或信号互连层。 屏蔽层位于电阻器组和/或信号互连层所在的区域的上方和/或下方。

公开(公告)号：US06331462B1

公开(公告)日：2001-12-18

申请号：US09453807

申请日：1999-12-03

申请人： Tatsuo Kasaoka ,  Atsushi Hachisuka ,  Shinya Soeda

发明人： Tatsuo Kasaoka ,  Atsushi Hachisuka ,  Shinya Soeda

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10873

摘要： A semiconductor substrate is arranged to have a DRAM area in which to form at a high density gate electrodes of transistors serving as DRAM components, and a peripheral circuit area in which to form at a relatively low density gate electrodes of transistors as peripheral circuit components. A resist film is formed in corresponding relation to the gate electrodes of the DRAM. After an insulating film is etched, a resist film is formed in corresponding relation to the gate electrodes of the peripheral circuits. A conductive layer is then etched while the resist film and insulating film left in the DRAM area are being used as masks, whereby the gate electrodes are formed in the DRAM area and peripheral circuit area.

摘要翻译： 半导体衬底被布置成具有在作为DRAM部件的晶体管的高密度栅电极形成的DRAM区域，以及在相对低密度的晶体管的栅极形成外围电路部件的外围电路区域。 以与DRAM的栅电极对应的关系形成抗蚀剂膜。 在蚀刻绝缘膜之后，以与外围电路的栅电极对应的关系形成抗蚀剂膜。 然后蚀刻导电层，同时将残留在DRAM区域中的抗蚀剂膜和绝缘膜用作掩模，由此在DRAM区域和外围电路区域中形成栅电极。

公开(公告)号：US5892291A

公开(公告)日：1999-04-06

申请号：US670313

申请日：1996-06-27

申请人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

发明人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

IPC分类号： G03F1/36 ,  G03F1/42 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027 ,  H05K1/02 ,  H01L23/544

CPC分类号： G03F7/706 ,  G03F7/70633 ,  Y10T428/24802 ,  Y10T428/24917

摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

摘要翻译： 本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件， 以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。 第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案 。 因此，可以提供考虑到像差影响的配准精度测量标记。

公开(公告)号：US06607964B2

公开(公告)日：2003-08-19

申请号：US09874110

申请日：2001-06-06

申请人： Hidenori Sato ,  Shinya Soeda

发明人： Hidenori Sato ,  Shinya Soeda

IPC分类号： H01L2120

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/10873

摘要： A first silicide protection film is deposited on a silicon substrate, a first resist pattern having an opening at a prescribed position is formed, a portion of the first silicide protection film exposed from the opening of the first resist pattern is removed to form a first opening in the first silicide protection film, an N+ diffusion layer is formed in a portion of the silicon substrate exposed from the first opening, the first resist pattern is removed, and a metallic film is deposited to form a first silicide layer on the N+ diffusion layer according to a silicide process. Thereafter, a second silicide protection film is deposited, a second resist pattern having an opening at a prescribed position is formed, portions of the first and second silicide protection films exposed from the opening of the second resist pattern are removed to form a second opening in the first and second silicide protection films, a P+ diffusion layer is formed in a portion of the silicon substrate exposed from the second opening, the second resist pattern is removed, and a metallic film is deposited to form a second silicide layer on the P+ diffusion layer according to the silicide process. Therefore, silicide layers having characteristics optimum to the diffusion layers can be formed, and the number of mask matching operations can be reduced.

公开(公告)号：US06388295B1

公开(公告)日：2002-05-14

申请号：US09663717

申请日：2000-09-18

申请人： Tomohiro Yamashita ,  Yoshinori Okumura ,  Atsushi Hachisuka ,  Shinya Soeda

发明人： Tomohiro Yamashita ,  Yoshinori Okumura ,  Atsushi Hachisuka ,  Shinya Soeda

IPC分类号： H01L2976

CPC分类号： H01L21/823493 ,  H01L21/761 ,  H01L27/10897

摘要： The semiconductor device has a triple well structure. The triple well and other wells have impurity concentration distributions in the depth direction, which are determined in accordance with required function. Thereby, the required performances such as suppression of a leak current can be achieved even in a miniaturized structure.

摘要翻译： 半导体器件具有三重阱结构。 三井等井在深度方向具有杂质浓度分布，根据所需的功能确定。 因此，即使在小型化结构中也能够实现抑制漏电流等所需的性能。

公开(公告)号：US06218235B1

公开(公告)日：2001-04-17

申请号：US09542876

申请日：2000-04-04

申请人： Atsushi Hachisuka ,  Hiroyasu Nohsoh ,  Shinya Soeda

发明人： Atsushi Hachisuka ,  Hiroyasu Nohsoh ,  Shinya Soeda

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/10894

摘要： A method of manufacturing a semiconductor device having a memory device and a logic device on the same semiconductor substrate is provided without reducing reliability of the semiconductor device and making a manufacturing process unnecessarily complicated. A silicon oxide film which serves as a salicide protection film in the logic device formation region is subjected to wet isotropic etching. The process completely removes the silicon oxide film in the memory device formation region. Thus, the silicon oxide film is left only in a prescribed portion in the logic device formation region. As a result, the silicon oxide film is not left on an inner wall of a recess formed by a silicon nitride film between gate electrodes. Consequently, a good self alignment contact opening is formed toward a source/drain region in the memory device formation region.

摘要翻译： 在不降低半导体器件的可靠性并使制造工艺不必要地复杂的情况下，提供具有在同一半导体衬底上的存储器件和逻辑器件的半导体器件的制造方法。 在逻辑器件形成区域中用作硅化物保护膜的氧化硅膜经受湿均匀蚀刻。 该过程完全去除存储器件形成区域中的氧化硅膜。 因此，氧化硅膜仅留在逻辑器件形成区域中的规定部分。 结果，氧化硅膜不留在由栅电极之间的氮化硅膜形成的凹部的内壁上。 因此，存储器件形成区域中的源极/漏极区域形成良好的自对准接触开口。

公开(公告)号：US06680539B2

公开(公告)日：2004-01-20

申请号：US09558269

申请日：2000-04-25

申请人： Hiroyasu Nohsoh ,  Hiroki Shinkawata ,  Shinya Soeda

发明人： Hiroyasu Nohsoh ,  Hiroki Shinkawata ,  Shinya Soeda

IPC分类号： H01L2348

CPC分类号： H01L23/5283 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： Patterns to be included in a multi-layer wiring structure of a semiconductor device are designed layer by layer. Functional patterns 92 necessary for implementing functions of the semiconductor device are formed first. A plurality of types of dummy patterns 96 and 98 having different sizes are then designed in free regions not occupied by the functional patterns. While the dummy patterns are being designed, the largest possible number of free regions 94 are extracted followed by as many smaller free regions 97 as possible. The dummy patterns 98 are laid out in the extracted free regions.

摘要翻译： 逐层设计包含在半导体器件的多层布线结构中的图案。 首先形成实现半导体器件的功能所需的功能图案92。 然后在不被功能图案占据的自由区域中设计具有不同尺寸的多种类型的虚拟图案96和98。 当设计虚拟图案时，提取最大可能数量的自由区域94，随后抽取尽可能多的较小的自由区域97。 虚拟图案98布置在提取的自由区域中。

公开(公告)号：US06670680B2

公开(公告)日：2003-12-30

申请号：US09845291

申请日：2001-05-01

申请人： Hiroyasu Nohsoh ,  Shinya Soeda

发明人： Hiroyasu Nohsoh ,  Shinya Soeda

IPC分类号： H01L2976

CPC分类号： H01L21/823871 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823878

摘要： A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.

摘要翻译： 根据本发明的双栅型CMOS器件包括在主表面具有沟槽的硅衬底和通过栅极绝缘膜在主表面上形成的多晶硅膜和硅化钨膜的栅电极。 多晶硅膜具有掺杂有p型杂质的第一部分，掺杂有n型杂质的第二部分和沟槽内的第一部分和第二部分连接的连接部分，以及部分硅化钨膜位于 上面的连接部分被去除。

公开(公告)号：US06355387B1

公开(公告)日：2002-03-12

申请号：US08562019

申请日：1995-11-22

申请人： Masato Fujinaga ,  Shinya Soeda

发明人： Masato Fujinaga ,  Shinya Soeda

IPC分类号： H01L21302

CPC分类号： G03F1/70

摘要： A technique of correcting a mask pattern without alleviating the design rule or measuring all contact hole diameters. Undulations are inspected in a region for forming contact holes (step S3). On the basis of the surface shape (undulations) determined at step S3, the contact hole diameter is predicted in the case of use of the mask hole diameter fabricated at step S1 (step S4). On the basis of the result of prediction, the mask pattern M is corrected to mask patter M′ according to the mask hole diameter (step S5).

摘要翻译： 校正掩模图案而不减轻设计规则或测量所有接触孔直径的技术。 在用于形成接触孔的区域中检查凹凸（步骤S3）。 基于在步骤S3中确定的表面形状（起伏），在使用在步骤S1中制造的掩模孔直径的情况下，预测接触孔直径（步骤S4）。 基于预测结果，根据掩模孔直径对掩模图案M进行修正以掩模图案M'（步骤S5）。

公开(公告)号：US06323560B1

公开(公告)日：2001-11-27

申请号：US09492750

申请日：2000-01-27

申请人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

发明人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

IPC分类号： H01L2358

CPC分类号： G03F7/706 ,  G03F7/70633 ,  Y10T428/24802 ,  Y10T428/24917

摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

摘要翻译： 本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件， 以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。 第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案 。 因此，可以提供考虑到像差影响的配准精度测量标记。