-
1.发明授权System switching method and apparatus without loss of signal in cell switching system of asynchronous transfer mode 失效异步传输模式小区交换系统中系统切换方式和设备信号丢失
公开(公告)号：US5283782A
公开(公告)日：1994-02-01
申请号：US745332
申请日：1991-08-15
CPC分类号： H04L49/105 , H04L49/153 , H04L49/552 , H04Q11/0478 , H04L2012/5627 , H04L49/1515
摘要： In a communication apparatus using an asynchronous transfer mode, there is provided a system switching method, and apparatus, without loss of signal for performing cell multiplexing or cell switching in a duplex system including a primary system and a standby system. In system switching, control information for switching between the primary system and the standby system is prepared. When a cell is inputted to the communication apparatus, the prepared control information is appended in a header portion of the cell. The cell with control information appended thereto is transmitted to the duplex system including the primary system and the standby system. On the basis of the control information, cell transfer of each system is controlled.
摘要翻译： 在使用异步传送模式的通信装置中，提供了一种系统切换方法和装置，在包括主系统和备用系统的双工系统中，不丢失用于进行小区复用或小区切换的信号。 在系统切换中，准备用于在主系统和备用系统之间切换的控制信息。 当单元被输入到通信设备时，所准备的控制信息被附加在单元的报头部分中。 具有附加控制信息的信元被发送到包括主系统和备用系统的双工系统。 在控制信息的基础上，控制每个系统的单元传送。
-
2.发明授权Shared buffer memory type ATM communication system and method with a broadcast facility 失效共享缓冲存储器类型ATM通信系统和方法与广播设施
公开(公告)号：US5394397A
公开(公告)日：1995-02-28
申请号：US38615
申请日：1993-03-29
IPC分类号： H04M3/42 , H04L12/18 , H04L12/761 , H04L12/931 , H04L12/951 , H04Q3/52 , H04Q11/04 , H04L12/56 , H04J3/26 , H04L12/48
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/309
摘要： An ATM switching system which includes an input interface which is provided every incoming line and serves to convert header information of each input cell into internal routing information, a shared buffer memory and a cell writing control unit which forms normal cell list structures, which are prepared in correspondence to outgoing lines and in which a plurality of normal cells are chained together with their next addresses, and a broadcast cell list structure, in which a plurality of broadcast cells are chained together with their next addresses, in the shared buffer memory, and serves to add successively the input cells to ones of the list structures, which are selected in correspondence to respective internal routing information. The invention also includes a cell reading control unit which serves to fetch selectively the cell from the list structures formed in the shared buffer memory to distribute the cell thus fetched to the associated outgoing lines. The cell reading control unit includes a broadcast destination table for "storing broadcast destination specifying information for specifying the outgoing lines, through which the broadcast cell is to be output, using a bit pattern, in correspondence to the internal routing information of the broadcast cell".
摘要翻译： 一种ATM交换系统，其包括为每条输入线路提供的输入接口，用于将每个输入单元的头信息转换为内部路由信息，共享缓冲存储器和形成正常小区列表结构的小区写入控制单元，其被准备 对应于输出线，并且其中多个正常小区与其下一个地址一起链接在一起，以及广播小区列表结构，其中多个广播小区与其下一个地址一起连接在共享缓冲存储器中，以及 用于将输入单元连续地添加到与各个内部路由信息相对应地选择的列表结构中的一个。 本发明还包括一个单元读取控制单元，用于从形成在共享缓冲存储器中的列表结构中选择性地提取单元，以将由此提取的单元分配到相关联的输出行。 小区读取控制单元包括：广播目的地表，用于根据广播小区的内部路由信息，使用位模式存储用于指定要输出广播小区的出行的广播目的地指定信息; 。
-
公开(公告)号：US5612959A
公开(公告)日：1997-03-18
申请号：US86088
申请日：1993-07-06
申请人： Akihiko Takase , Shiro Tanabe , Noboru Endo , Ryoji Takeyari , Yusuke Mishina , Toshiya Oouchi , Junichirou Yanagi
发明人： Akihiko Takase , Shiro Tanabe , Noboru Endo , Ryoji Takeyari , Yusuke Mishina , Toshiya Oouchi , Junichirou Yanagi
CPC分类号： H04L12/1836 , H04L12/4608 , H04L12/66 , H04Q11/0478 , H04L2012/5615 , H04L2012/5619 , H04L2012/5642
摘要： Distributed LANs are connected to a wide area network through terminal adapters, which are interconnected by virtual circuits to form a logical bus network. Each terminal adapter copies cells received through the virtual circuit that is allocated for multicasting, and transfers the copied cells to the adjacent terminal adapters via preset virtual circuits. The terminal adapters assemble a part or all of the transmitted message from the received cells and, according to the contents of the assembled message, transfer the copies of the cells to the adjacent terminal adapters through predetermined virtual circuits.
摘要翻译： 分布式LAN通过终端适配器连接到广域网，虚拟电路通过终端适配器互连，形成逻辑总线网络。 每个终端适配器复制通过分配给组播的虚拟电路接收的小区，并通过预置的虚拟电路将复制的小区传送到相邻的终端适配器。 终端适配器从接收到的小区组合部分或全部发送的消息，并且根据组合消息的内容，通过预定的虚拟电路将小区的副本传送到相邻的终端适配器。
-
4.发明授权
公开(公告)号：US5657321A
公开(公告)日：1997-08-12
申请号：US566702
申请日：1995-12-04
CPC分类号： H04Q11/0478 , H04L12/2852 , H04L12/437 , H04L69/40 , H04L2012/561 , H04L2012/5612 , H04L2012/5613 , H04L2012/562 , H04L2012/5625 , H04L2012/5627 , H04L2012/5674
摘要： A looped bus system includes several nodes connected by unidirectional buses having opposite directions of signal transmission. The head of bus function for each bus is located at a node different from the head of bus function for the other bus. The head of bus function for each bus is located at the same node as the termination of bus function for the other bus. As a result, the buses can be reconfigured and nodes can be added freely by the use of a bus portion that is unused in the looped bus under normal condition.
摘要翻译： 环路总线系统包括通过具有相反方向的信号传输的单向总线连接的若干节点。 每个总线的总线功能头位于与其他总线的总线功能头不同的节点上。 每个总线的总线功能头位于与其他总线的总线功能终止相同的节点。 结果，可以重新配置总线，并且可以通过使用在正常条件下在循环总线中未使用的总线部分来自由地添加节点。
-
公开(公告)号：US5280475A
公开(公告)日：1994-01-18
申请号：US745466
申请日：1991-08-14
IPC分类号： H04Q3/00 , H04L12/815 , H04L12/863 , H04L12/931 , H04L12/951 , H04Q11/04 , H04L12/56
CPC分类号： H04L12/5601 , H04L12/5602 , H04L49/108 , H04L49/255 , H04L49/3081 , H04Q11/0478 , H04L2012/568
摘要： A traffic shaping method and circuit of a packet switching system in which input packets having a fixed length and multiplexed on a plurality of inputs are multiplexed to be delivered on any output of a plurality of outputs, connects the input packet to a list structure using an address chain formed for each output, forms the list structure even for each line identifier provided in the packet, and assigns the identifier for each time slot of the output to take out the packet from the list structure, to thereby prevent the packet having the same identifier from being multiplexed and delivering to the output continuously.
摘要翻译： 一种分组交换系统的流量整形方法和电路，其中具有固定长度并在多个输入上复用的输入分组被多路复用以在多个输出的任何输出上传送，将输入分组连接到列表结构，使用 为每个输出形成的地址链，甚至对于分组中提供的每个行标识符也形成列表结构，并且分配输出的每个时隙的标识符以从列表结构中取出分组，从而防止具有相同的分组 标识符被多路复用并连续传送到输出。
-
公开(公告)号：US5155487A
公开(公告)日：1992-10-13
申请号：US664115
申请日：1991-03-04
CPC分类号： H04L1/0061 , H03M13/091 , H04L1/0043 , H04L2012/5674
摘要： In a cell delineation circuit, an input signal is converted into parallel signals, and a plurality of parallel signals (i.e. series of parallel signals) which are shifted one bit by one bit from each other are formed from those parallel signals. CRC (Cyclic Redundancy Check) calculations are executed in parallel for the plurality of parallel signals. A series in which a pattern to be calculated satisfies a CRC rule is determined from results of the CRC calculations, and this series is generated, thereby establishing a cell delineation.
摘要翻译： 在单元描绘电路中，输入信号被转换成并行信号，并且由这些并行信号形成彼此移位一比特的多个并行信号（即并行信号串）。 针对多个并行信号并行执行CRC（循环冗余校验）计算。 根据CRC计算的结果确定其中要计算的模式满足CRC规则的一系列，并且生成该系列，由此建立单元描绘。
-
7.发明授权
公开(公告)号：US5487062A
公开(公告)日：1996-01-23
申请号：US230152
申请日：1994-04-19
CPC分类号： H04Q11/0478 , H04L12/2852 , H04L12/437 , H04L69/40 , H04L2012/561 , H04L2012/5612 , H04L2012/5613 , H04L2012/562 , H04L2012/5625 , H04L2012/5627 , H04L2012/5674
摘要： A looped bus system includes several nodes connected by unidirectional buses having opposite directions of signal transmission. The head of bus function for each bus is located at a node different from the head of bus function for the other bus. The head of bus function for each bus is located at the same node as the termination of bus function for the other bus; As a result, the buses can be reconfigured and nodes can be added freely by the use of a bus portion that is unused in the looped bus under normal condition.
摘要翻译： 环路总线系统包括通过具有相反方向的信号传输的单向总线连接的若干节点。 每个总线的总线功能头位于与其他总线的总线功能头不同的节点上。 每个总线的总线功能头位于与其他总线终端总线功能相同的节点; 结果，可以重新配置总线，并且可以通过使用在正常条件下在循环总线中未使用的总线部分来自由地添加节点。
-
8.发明授权
公开(公告)号：US5315581A
公开(公告)日：1994-05-24
申请号：US744717
申请日：1991-08-14
IPC分类号： H04L1/22 , H04B1/74 , H04L12/70 , H04L12/801 , H04L12/911 , H04L29/14 , H04Q11/04 , H04L1/02
CPC分类号： H04L49/3081 , H04B1/74 , H04L69/40 , H04Q11/0478 , H04L2012/5627
摘要： A hit-less protection switching method and apparatus therefor for ATM transmission lines for selecting first cells from normal received signals and writing the same into a normal cell buffer, selecting second cells from emergency received signals and writing the same into an emergency cell buffer, reading the first cells from the normal cell buffer after a first delay time, reading the second cells from the emergency cell buffer after a second delay time, comparing the contents of the first cell with the contents of the second cell and changing the difference between the first delay time and the second delay time, when a state of discrepancy between the contents of the first cell and the contents of the second cell is continuously detected for a predetermined time, to dissolve the state of discrepancy, and selecting one of the cells read from the normal cell buffer and the emergency cell buffer with a delay as communications information.
摘要翻译： 一种无线保护切换方法及其装置，用于ATM传输线路，用于从正常接收信号中选择第一小区并将其写入正常小区缓冲器，从紧急接收信号中选择第二小区并将其写入紧急小区缓冲器，读取 在第一延迟时间之后，来自正常单元缓冲器的第一个单元，在第二延迟时间之后从紧急单元缓冲器读取第二单元，将第一单元的内容与第二单元的内容进行比较，并且改变第一单元 延迟时间和第二延迟时间，当在预定时间内连续检测到第一单元的内容与第二单元的内容之间的差异的状态以解决差异的状态时，并且从 正常小区缓冲区和具有延迟的紧急小区缓冲区作为通信信息。
-
公开(公告)号：US5768274A
公开(公告)日：1998-06-16
申请号：US678659
申请日：1996-07-11
申请人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
发明人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
CPC分类号： H04J3/247 , H04L7/048 , H04Q11/0478 , H04L2007/045 , H04L2012/5616 , H04L2012/5647 , H04L2012/5652 , H04L2012/5672 , H04L2012/5674
摘要： A cell multiplexer includes a multiplexing unit for time-divisionally multiplexing ATM cell signals given from a plurality of input lines, a write controller for storing cell signals outputted from the multiplexing unit in a buffer memory successively correspondingly to the input lines, a read controller for reading the cell signals stored in the buffer memory from the buffer memory in the form of data blocks synchronized with an ATM cell structure, and a cell delineation controller for detecting delineation states of the data blocks read out from the buffer memory, notifying the read controller of delineation control information corresponding to a result of the detection and transmitting data blocks read out in synchronism with a predetermined cell structure to the output line selectively, wherein the read controller determines the read beginning addresses of data blocks to be read out nextly correspondingly to the input lines on the basis of the delineation control information notified by the cell delineation controller.
-
公开(公告)号：US5570368A
公开(公告)日：1996-10-29
申请号：US409691
申请日：1995-03-24
申请人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
发明人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
CPC分类号： H04J3/247 , H04L7/048 , H04Q11/0478 , H04L2007/045 , H04L2012/5616 , H04L2012/5647 , H04L2012/5652 , H04L2012/5672 , H04L2012/5674
摘要： A cell multiplexer includes a multiplexing unit for time-divisionally multiplexing ATM cell signals given from a plurality of input lines, a write controller for storing cell signals outputted from the multiplexing unit in a buffer memory successively correspondingly to the input lines, a read controller for reading the cell signals stored in the buffer memory from the buffer memory in the form of data blocks synchronized with an ATM cell structure, and a cell delineation controller for detecting delineation states of the data blocks read out from the buffer memory, notifying the read controller of delineation control information corresponding to a result of the detection and transmitting data blocks read out in synchronism with a predetermined cell structure to the output line selectively, wherein the read controller determines the read beginning addresses of data blocks to be read out nextly correspondingly to the input lines on the basis of the delineation control information notified by the cell delineation controller.
摘要翻译： 单元多路复用器包括用于对多个输入线提供的ATM信元进行时分多路复用的复用单元，用于将连续相应于输入线的多路复用单元输出的单元信号存储在缓冲存储器中的读控制器， 以与ATM单元结构同步的数据块的形式从缓冲存储器读取存储在缓冲存储器中的单元信号;以及单元描绘控制器，用于检测从缓冲存储器读出的数据块的描画状态，通知读取控制器 选择对应于与预定单元结构同步地读出的数据块的检测结果对应的描画控制信息到所述输出行，其中，所述读取控制器确定与所述读取控制信息相对应地读出的数据块的读取开始地址 输入线根据描绘控制信息通知 由细胞描绘控制器编辑。
-
-
-
-
-
-
-
-
-
搜索结果
69 条记录 (耗时 0.019 秒)