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    Method of making semiconductor device
    1.
    发明授权
    Method of making semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US4247373A

    公开(公告)日：1981-01-27

    申请号：US47931

    申请日：1979-06-12

    申请人： Akio Shimano ,  Hiromitsu Takagi

    发明人： Akio Shimano ,  Hiromitsu Takagi

    IPC分类号： H01L21/3063 ,  H01L21/311 ,  H01L21/316 ,  H01L21/329 ,  H01L21/338 ,  C25D11/02 ,  C25D11/32

    CPC分类号： H01L29/66166 ,  H01L21/02241 ,  H01L21/02258 ,  H01L21/30635 ,  H01L21/31111 ,  H01L21/31675 ,  H01L21/31679 ,  H01L29/66863

    摘要： An epitaxial layer having a specified conductivity type formed on a semiinsulative or high resistivity semiconductor substrate or insulative substrate is anodized (anodically oxidized) by a predetermined D.C. current under an illumination of light of a predetermined intensity, thereby a depletion layer is formed beneath an oxide layer, which is formed by the anodizing, and the anodizing ceases in areas where the bottom face of the depletion layer reaches the semiinsulative or high resistivity semiconductor substrate or insulative substrate thus retaining a layer of highly uniform thickness layer of the epitaxial grown layer on the substrate.

    摘要翻译： 在半导体或半导体衬底或绝缘衬底上形成的具有特定导电类型的外延层在预定强度的光的照射下被预定的直流电流阳极氧化（阳极氧化），从而在氧化物之下形成耗尽层 层，其通过阳极氧化形成，并且阳极氧化停止在耗尽层的底面到达半绝缘或高电阻率半导体衬底或绝缘衬底的区域中，从而将外延生长层的高度均匀的厚度层的层保持在 基质。

    Mesfet latch circuit
    2.
    发明授权
    Mesfet latch circuit 失效
    Mesfet锁存电路

    公开(公告)号：US4883985A

    公开(公告)日：1989-11-28

    申请号：US117367

    申请日：1987-10-28

    申请人： Shin Katsu ,  Shutaro Nambu ,  Akio Shimano

    发明人： Shin Katsu ,  Shutaro Nambu ,  Akio Shimano

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356034 ,  H03K3/356043 ,  H03K3/35606 ,  H03K3/356069

    摘要： An FET circuit suitable for a latch has a pair of inverters. The input stage FET of each of the inverters is connected such that the gate electrode thereof is connected to receive an output signal of the FET of the other inverter through a circuit having an FET and at least a diode. The sources of the input stage FETs are connected to a common connection point, and a current source arrangement such as a resistor is connected between the common connection point and a power supply terminal. The circuit provides an extended allowable range of the effective threshold voltage V.sub.T and has small power consumption.

    摘要翻译： 适用于锁存器的FET电路具有一对反相器。 每个反相器的输入级FET被连接成使得其栅电极连接以通过具有FET和至少二极管的电路接收另一逆变器的FET的输出信号。 输入级FET的源极连接到公共连接点，并且在公共连接点和电源端子之间连接诸如电阻器的电流源装置。 电路提供有效阈值电压VT的扩展允许范围，功耗小。