公开(公告)号：US4247373A

公开(公告)日：1981-01-27

申请号：US47931

申请日：1979-06-12

申请人： Akio Shimano ,  Hiromitsu Takagi

发明人： Akio Shimano ,  Hiromitsu Takagi

IPC分类号： H01L21/3063 ,  H01L21/311 ,  H01L21/316 ,  H01L21/329 ,  H01L21/338 ,  C25D11/02 ,  C25D11/32

CPC分类号： H01L29/66166 ,  H01L21/02241 ,  H01L21/02258 ,  H01L21/30635 ,  H01L21/31111 ,  H01L21/31675 ,  H01L21/31679 ,  H01L29/66863

摘要： An epitaxial layer having a specified conductivity type formed on a semiinsulative or high resistivity semiconductor substrate or insulative substrate is anodized (anodically oxidized) by a predetermined D.C. current under an illumination of light of a predetermined intensity, thereby a depletion layer is formed beneath an oxide layer, which is formed by the anodizing, and the anodizing ceases in areas where the bottom face of the depletion layer reaches the semiinsulative or high resistivity semiconductor substrate or insulative substrate thus retaining a layer of highly uniform thickness layer of the epitaxial grown layer on the substrate.

摘要翻译： 在半导体或半导体衬底或绝缘衬底上形成的具有特定导电类型的外延层在预定强度的光的照射下被预定的直流电流阳极氧化（阳极氧化），从而在氧化物之下形成耗尽层 层，其通过阳极氧化形成，并且阳极氧化停止在耗尽层的底面到达半绝缘或高电阻率半导体衬底或绝缘衬底的区域中，从而将外延生长层的高度均匀的厚度层的层保持在 基质。

公开(公告)号：US5883411A

公开(公告)日：1999-03-16

申请号：US982068

申请日：1992-11-23

申请人： Daisuke Ueda ,  Hiromitsu Takagi

发明人： Daisuke Ueda ,  Hiromitsu Takagi

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66734

摘要： An insulated gate FET such as a power MOS FET is made by forming a rectangular parallelepiped-shaped recess in a direction that the side walls of the recess make 45.degree. angle against the direction of the silicon substrate having (100) plane as principal surface, and the vertical side walls of (010) or (001) planes are used as channel region of the insulated gate FET, thereby assuring a large electron mobility in the channel, hence low channel resistance suitable for high power operation.

摘要翻译： 通过在凹部的侧壁相对于具有（100）面的硅衬底的<100>方向成45°角的方向上形成长方体形状的凹槽来形成诸如功率MOS FET的绝缘栅极FET，如 （010）或（001）面的垂直侧壁用作绝缘栅FET的沟道区，从而确保沟道中的电子迁移率大，因此适用于大功率操作的低通道电阻。

公开(公告)号：US20110076202A1

公开(公告)日：2011-03-31

申请号：US12994504

申请日：2008-10-23

申请人： Takahito Asanuma ,  Hiromitsu Takagi ,  Isamu Yashima ,  Akira Abe

发明人： Takahito Asanuma ,  Hiromitsu Takagi ,  Isamu Yashima ,  Akira Abe

IPC分类号： B01J23/50 ,  B01D53/94

CPC分类号： B01D53/94 ,  B01D39/2068 ,  B01D53/944 ,  B01D53/96 ,  B01D2255/104 ,  B01D2255/20715 ,  B01D2255/9207 ,  B01D2258/012 ,  B01J21/066 ,  B01J23/50 ,  B01J35/1009 ,  B01J35/1014 ,  B01J37/08 ,  F01N3/035 ,  F01N2370/00

摘要： Provided is a particulate combustion catalyst including a carrier formed of monoclinic zirconium oxide particles, and metallic Ag or Ag oxide, which serves as a catalyst component and is supported on the carrier, wherein the amount of the catalyst component is 0.5 to 10 mass %, as reduced to metallic Ag, on the basis of the mass of the carrier, and preferably, the catalyst has a BET specific surface area of 8 to 21 m2/g. Also provided are a particulate filter coated with the particulate combustion catalyst; and an exhaust gas cleaning apparatus including a particulate filter coated with the particulate combustion catalyst.

摘要翻译： 本发明提供一种颗粒燃烧催化剂，其包括由单斜晶氧化锆颗粒形成的载体和用作催化剂组分并负载在载体上的金属Ag或Ag氧化物，其中催化剂组分的量为0.5至10质量％ 还原为金属Ag，基于载体的质量，优选催化剂的BET比表面积为8〜21m 2 / g。 还提供了涂覆有颗粒燃烧催化剂的颗粒过滤器; 以及包括涂覆有颗粒燃烧催化剂的颗粒过滤器的废气净化装置。

公开(公告)号：US4194927A

公开(公告)日：1980-03-25

申请号：US923689

申请日：1978-07-11

申请人： Hiromitsu Takagi ,  Gota Kano ,  Iwao Teramoto

发明人： Hiromitsu Takagi ,  Gota Kano ,  Iwao Teramoto

IPC分类号： H01L21/3105 ,  H01L21/324 ,  H01L7/36 ,  H01L7/44

CPC分类号： H01L21/3105 ,  H01L21/3245

摘要： In the process of forming a thermal oxide film or heat treatment of an oxide film in making a semiconductor device comprising a compound semiconductor of arsenic, the semiconductor is handled in an atmosphere containing arsenic oxide vapor in order to prevent evaporation of the arsenic tri-oxide in the thermal oxidation film or the oxide film under heat treatment, thereby to form a thermal oxide film having good chemical stability and good electrical characteristics, or to improve the oxide film so as to have good chemical stability and good electrical characteristics.

摘要翻译： 在制造包含砷化合物半导体的半导体器件中形成热氧化膜或氧化膜的热处理的过程中，在含有氧化砷蒸汽的气氛中处理半导体，以防止三氧化砷的蒸发 在热氧化膜或氧化膜中进行热处理，从而形成具有良好的化学稳定性和良好的电特性的热氧化膜，或改善氧化膜以具有良好的化学稳定性和良好的电特性。

公开(公告)号：US20070009496A1

公开(公告)日：2007-01-11

申请号：US10580248

申请日：2004-11-19

申请人： Mimi Adachi ,  Keiichi Nakayama ,  Shigetaka Kitajima ,  Hiromitsu Takagi

发明人： Mimi Adachi ,  Keiichi Nakayama ,  Shigetaka Kitajima ,  Hiromitsu Takagi

IPC分类号： A61K48/00 ,  C12N15/00 ,  C12N5/08 ,  C12N15/86 ,  C12N15/88

CPC分类号： C12N5/0657 ,  A61K31/7088 ,  A61K35/12 ,  A61K48/00 ,  C07K14/4738 ,  C12N9/1205 ,  C12N2510/00

摘要： The proliferation of cardiomyocytes is induced by expressing cyclin and CDK in the cardiomyocytes, and by suppressing the function or action of a Cip/Kip family protein or inhibiting the production of a Cip/Kip family protein. Among the Cip/Kip family proteins, it is preferable to suppress the function of p27KiP1 or inhibiting the production thereof. As a recombinant vector to be used therefor, there is provided a vector comprising: (1) a cyclin gene; (2) a cyclin-dependent kinase gene; and (3) one or a plurality selected from the group consisting of a gene encoding a factor that inhibits the function or action of a Cip/Kip family protein and a nucleic acid sequence that inhibits the production of Cip/Kip family protein.

摘要翻译： 通过在心肌细胞中表达细胞周期蛋白和CDK，并通过抑制Cip / Kip家族蛋白的功能或作用或抑制Cip / Kip家族蛋白的产生来诱导心肌细胞的增殖。 在Cip / Kip家族蛋白质中，优选抑制p27 KiP1的功能或抑制其生产。 作为用于其的重组载体，提供了载体，其包含：（1）细胞周期蛋白基因; （2）细胞周期蛋白依赖性激酶基因; 和（3）选自由编码抑制Cip / Kip家族蛋白的功能或作用的因子的基因和抑制Cip / Kip家族蛋白的产生的核酸序列组成的组中的一种或多种。

公开(公告)号：US4351099A

公开(公告)日：1982-09-28

申请号：US149621

申请日：1980-05-12

申请人： Hiromitsu Takagi ,  Shotaro Umebachi ,  Gota Kano ,  Iwao Teramoto

发明人： Hiromitsu Takagi ,  Shotaro Umebachi ,  Gota Kano ,  Iwao Teramoto

IPC分类号： H01L21/033 ,  H01L21/337 ,  H01L29/80 ,  H01L29/808 ,  H01L21/31 ,  H01L21/225 ,  H01L21/265

CPC分类号： H01L29/66909 ,  H01L21/033 ,  H01L29/80 ,  H01L29/808

摘要： A novel self-align type method of making an FET with a very short gate length and a good high frequency characteristic, and a low noise characteristic, the method comprising the steps of:forming on a silicon epitaxial layer (13) of n-type conductivity a doped oxide film (14) containing boron as an impurity to give p-type conductivity,forming a mask (15a, 16a) containing Si.sub.3 N.sub.4 film and having a width larger than that of a gate region (19) to be formed on said n-type epitaxial layer (13),etching said doped oxide film (14) by utilizing said mask (15a, 16a) as an etching mask to expose surface of said silicon crystal layer (13) in a manner that sides of the part of said doped oxide film (14) covered by said mask (15, 16a) are side-etched by a predetermined width,ion-implanting an impurity of said first conductivity type into said n-type epitaxial layer (13) by utilizing said mask as implanting mask, andcarrying out a heat treating thereby diffusing said second conductivity type impurity from said doped oxide film (14) retained only under said mask into said n-type epitaxial layer (13) to form said gate region (19) and driving said ion-implanted first conductivity type impurity into said silicon crystal layer (13) to form a source region (17) and a drain region (18).

摘要翻译： 一种制造具有非常短的栅极长度和良好的高频特性以及低噪声特性的FET的新型自对准型方法，该方法包括以下步骤：在n型硅外延层（13）上形成 电导率为含有硼作为杂质的掺杂氧化物膜（14）以产生p型导电性，形成包含Si 3 N 4膜的掩模（15a，16a），其宽度大于所述栅极区域（19）的宽度 通过利用所述掩模（15a，16a）作为蚀刻掩模蚀刻所述掺杂氧化物膜（14），以使得所述硅晶体层（13）的所述一部分的侧面 将由所述掩模（15,16a）覆盖的所述掺杂氧化物膜（14）以预定宽度进行侧蚀刻，通过利用所述掩模将所述第一导电类型的杂质离子注入所述n型外延层（13） 植入掩模，并进行热处理，从而扩散所述第二导电型不动杆 将所述掺杂氧化物膜（14）保留在所述掩模内的所述n型外延层（13）中以形成所述栅极区域（19）并将所述离子注入的第一导电类型杂质驱动到所述硅晶体层（13）中， 以形成源极区（17）和漏极区（18）。

公开(公告)号：US3989962A

公开(公告)日：1976-11-02

申请号：US555676

申请日：1975-03-05

申请人： Hiromitsu Takagi ,  Gota Kano

发明人： Hiromitsu Takagi ,  Gota Kano

IPC分类号： G11C11/41 ,  H02H9/02 ,  H03B7/06 ,  H03H11/52 ,  H03K17/082 ,  H03K17/58 ,  H03K17/687 ,  H03K4/83 ,  H02H9/00 ,  H03K3/353 ,  H03K17/72

CPC分类号： H03K17/0826 ,  H02H9/025

摘要： Both source-electrodes (S1 and S2) or both drain-electrodes of a pair of field-effect transistors (FETs) (F1 and F2) of n-channel type and p-channel type, respectively, both to be electrically actuated in a depletion mode are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, through a variable resistance element (F3) inbetween, whereby the pair of FETs (F1 and F3) are series-connected through the variable resistance element (F3) inbetween, the gate-electrode (g1 or g2) of each FET is connected to the drain-electrode (d2 or d1) or the source-electrode of the other FET (F2 or F1) that is not connected to the variable resistance element (F3), and a pair of external terminals (1 and 2) are connected to said gate electrodes (g1, g2) those are connected to said drain electrodes (d2 and d1) or source electrodes.When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon, and a curve of voltage-current characteristic changes responding to the value of control signal to the variable resistance element.Since this device is a negative resistance of variable characteristic this device can be utilized for switching, signal relaying, memorization and other various controlling or data processing uses.

摘要翻译： 分别在n沟道型和p沟道型的一对场效应晶体管（FET）（F1和F2）中的两个源电极（S1和S2）或两个漏电极都被电致动 耗尽模式彼此连接，或者一个FET的源极和另一个FET的漏极通过其间的可变电阻元件（F3）彼此连接，由此一对FET（F1和F3）串联连接， 通过可变电阻元件（F3）连接，每个FET的栅电极（g1或g2）连接到漏电极（d2或d1）或另一个FET（F2或F1）的源电极， 未连接到可变电阻元件（F3），并且一对外部端子（1和2）连接到与所述漏电极（d2和d1）或源电极连接的所述栅电极（g1，g2）。