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6 条记录 (耗时 0.018 秒)

    Vertical type semiconductor device and gate structure
    1.
    发明授权
    Vertical type semiconductor device and gate structure 失效
    垂直型半导体器件和栅极结构

    公开(公告)号：US5798550A

    公开(公告)日：1998-08-25

    申请号：US469622

    申请日：1995-06-06

    申请人： Akira Kuroyanagi ,  Masami Yamaoka ,  Yoshifumi Okabe ,  Yasuaki Tsuzuki ,  Yutaka Tomatsu

    发明人： Akira Kuroyanagi ,  Masami Yamaoka ,  Yoshifumi Okabe ,  Yasuaki Tsuzuki ,  Yutaka Tomatsu

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/66719 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/1095

    摘要： The present invention involves a vertical type semiconductor device whereby miniaturization and lowered ON resistance of a cell within the device can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meeting the demand for miniaturization of the cell while the distance between the channel regions which are diffused into the portions below the gate during double diffusion remains virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. While the width of the gate electrode is set to be smaller, the mask members used during double diffusion are attached to the side walls of the gate electrode, where their width allows the source region to diffuse to the portion under the gate. Accordingly, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.

    摘要翻译： 本发明涉及垂直型半导体器件，由此可以实现器件内的电池的小型化和降低的导通电阻，而不会损害器件的功能。 使栅电极的线宽变小以满足电池小型化的需要，而在双扩散期间扩散到栅极下方的沟道区域之间的距离实际上等于在较大单元尺寸的器件中的沟道区域之间的距离 具有低JFET电阻分量。 虽然栅电极的宽度设定得较小，但是在双扩散期间使用的掩模构件附接到栅电极的侧壁，其宽度允许源极区域扩散到栅极下方的部分。 因此，可以实现电池的小型化和降低的导通电阻，而不会损害器件的功能。

    Method for producing semiconductor device having DMOS and NMOS elements formed in the same substrate
    2.
    发明授权
    Method for producing semiconductor device having DMOS and NMOS elements formed in the same substrate 失效
    用于制造具有形成在同一衬底中的DMOS和NMOS元件的半导体器件的方法

    公开(公告)号：US5550067A

    公开(公告)日：1996-08-27

    申请号：US38953

    申请日：1993-03-29

    申请人： Akira Kuroyanagi ,  Yutaka Tomatsu ,  Yasuaki Tsuzuki

    发明人： Akira Kuroyanagi ,  Yutaka Tomatsu ,  Yasuaki Tsuzuki

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8236 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/66712 ,  H01L21/823456 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/1095 ,  H01L29/402

    摘要： An intelligent power element has integrated DMOS transistors and control elements such as NMOS transistors. Impurity concentration inside a channel well (4) of each DMOS transistor is denser than that at the surface thereof. This results in reducing the reach-through withstand voltage of the DMOS transistor to less than that of the NMOS transistor. As a result, a reach-through phenomenon occurs on the DMOS transistor having a higher allowable (withstand) current before it occurs on the NMOS transistor having a lower allowable current. To provide the same effect, the reach-through withstand voltage of the DMOS transistor may be decreased by forming an internal high concentration well (201) at an upper part of a deep main well (31) of the DMOS transistor. The well (201) is shallower than the main well (31) and does not extend under a gate electrode (71).

    摘要翻译： 智能功率元件集成了DMOS晶体管和诸如NMOS晶体管的控制元件。 每个DMOS晶体管的通道阱（4）内的杂质浓度比其表面处的浓度更致密。 这导致将DMOS晶体管的可达耐受电压降低到小于NMOS晶体管的耐受电压。 结果，在具有较低可允许电流的NMOS晶体管上发生之前，在具有较高允许（耐受）电流的DMOS晶体管上会发生到达现象现象。 为了提供相同的效果，可以通过在DMOS晶体管的深主阱（31）的上部形成内部高浓度阱（201）来降低DMOS晶体管的到达耐受电压。 井（201）比主井（31）浅，并且不在栅电极（71）下延伸。

    Method of producing a semiconductor device having accurate current detection
    3.
    发明授权
    Method of producing a semiconductor device having accurate current detection 失效
    制造具有精确电流检测的半导体器件的方法

    公开(公告)号：US5534454A

    公开(公告)日：1996-07-09

    申请号：US385553

    申请日：1995-02-08

    申请人： Yasuaki Tsuzuki ,  Akira Kuroyanagi ,  Toshiaki Nishizawa

    发明人： Yasuaki Tsuzuki ,  Akira Kuroyanagi ,  Toshiaki Nishizawa

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L29/7815 ,  H01L27/0248 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095

    摘要： A power DMOS semiconductor device is producible with standard processes and provides improved current detecting accuracy. The device involves main wells (41), subwells (42), and a line well (43), which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate (1) with well forming impurities. The line well surrounds the subwells with a predetermined distance away from the subwells, to relax an electric field on the surface of the substrate. Gate electrodes (71, 72) are patterned to form a line opening (10), which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.

    摘要翻译： 功率DMOS半导体器件可通过标准工艺生产，并提供改进的电流检测精度。 该装置包括主井（41），底孔（42）和一条管井（43），其独立于主井和下井。 这些阱通过掺杂具有良好形成杂质的半导体衬底（1）的表面而形成。 线条井围绕底孔以预定的距离离开底孔，以松弛基底表面上的电场。 栅电极（71,72）被图案化以形成围绕底孔的线路开口（10）。 当通过用形成孔的杂质掺杂衬底的表面来形成线时，线路开口用作掩模。 因此，线槽与相邻的底座之间的区域的宽度不会波动。

    Vertical type semiconductor with main current section and emulation current section
    4.
    发明授权
    Vertical type semiconductor with main current section and emulation current section 失效
    具有主电流部分和仿真电流部分的垂直型半导体

    公开(公告)号：US5410171A

    公开(公告)日：1995-04-25

    申请号：US038951

    申请日：1993-03-29

    申请人： Yasuaki Tsuzuki ,  Akira Kuroyanagi ,  Toshiaki Nishizawa

    发明人： Yasuaki Tsuzuki ,  Akira Kuroyanagi ,  Toshiaki Nishizawa

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/7815 ,  H01L27/0248 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095

    摘要： A power DMOS semiconductor device providing improved current detection accuracy can be produced using standard pocessess. The device includes main wells, subwells and a line well which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate with well-forming impurities. The line well surrounds the subwells at a predetermined distance away from the subwells to relax an electric field on the surface of the substrate. Gate electrodes are patterned to form a line opening which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well-forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.

    摘要翻译： 提供提高电流检测精度的功率DMOS半导体器件可以使用标准的方式产生。 该装置包括主井，下井和一条独立于主井和下井的线井。 这些阱通过掺杂具有良好形成杂质的半导体衬底的表面而形成。 线路井在距离底孔预定距离处围绕底孔，以松弛基底表面上的电场。 图案化栅电极以形成围绕底孔的线路开口。 线形开口用于通过用形成阱的杂质掺杂衬底的表面来形成线状物时用作掩模。 因此，线槽与相邻的底座之间的区域的宽度不会波动。