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公开(公告)号：US07697320B2
公开(公告)日：2010-04-13
申请号：US12122174
申请日：2008-05-16
IPC分类号： G11C11/40
CPC分类号： G11C11/412 , G11C11/419
摘要： In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided.
摘要翻译： 在具有第一和第二负载晶体管，第一和第二驱动晶体管以及第一和第二存取晶体管的存储单元中，设置在第一位线和第一存储器节点之间并具有栅极端子的第三存取晶体管 连接到第一列线和设置在第二位线和第二存储器节点之间并且具有连接到第二列线的栅极端子的第四存取晶体管。
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公开(公告)号：US20090016144A1
公开(公告)日：2009-01-15
申请号：US12122174
申请日：2008-05-16
IPC分类号： G11C8/08
CPC分类号： G11C11/412 , G11C11/419
摘要： In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided.
摘要翻译： 在具有第一和第二负载晶体管，第一和第二驱动晶体管以及第一和第二存取晶体管的存储单元中，设置在第一位线和第一存储器节点之间并具有栅极端子的第三存取晶体管 连接到第一列线和设置在第二位线和第二存储器节点之间并且具有连接到第二列线的栅极端子的第四存取晶体管。
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公开(公告)号：US20050002225A1
公开(公告)日：2005-01-06
申请号：US10879753
申请日：2004-06-30
IPC分类号： G11C11/417 , G11C7/10 , G11C7/12 , G11C7/18 , G11C11/41 , G11C11/419 , G11C11/00
CPC分类号： G11C7/1069 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C11/419 , G11C2207/002
摘要： A semiconductor memory device comprises a plurality of memory cell groups. Each memory cell group includes at least two memory cells. Each memory cell group includes a read section and a write section. The data of a memory cell is read from one bit line to a read global bit line through the read section. The write section is shared by at least two memory cells in the same memory cell group. Thus, writing of data in a memory cell is desirably achieved although the memory cell has a common 6-transistor structure.
摘要翻译： 半导体存储器件包括多个存储单元组。 每个存储单元组包括至少两个存储单元。 每个存储单元组包括读取部分和写入部分。 存储单元的数据通过读取部分从一个位线读取到读出的全局位线。 写入部分由相同存储器单元组中的至少两个存储器单元共享。 因此，尽管存储单元具有共同的6晶体管结构，但期望地将数据写入存储单元。
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公开(公告)号：US06982899B2
公开(公告)日：2006-01-03
申请号：US10752663
申请日：2004-01-08
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： A dummy bit line is provided between a pair of bit lines. The pair of bit lines is set at a power supply voltage and the dummy bit line is set at a ground voltage, and then the pair of bit lines and the dummy bit line are equalized. When a word line is activated in subsequent read operation, the pair of bit lines is at an intermediate potential lower than the power supply voltage, so that an apparent current drive capability of an access transistor decreases, and the static noise margin of a memory cell increases.
摘要翻译： 在一对位线之间提供虚拟位线。 一对位线被设定为电源电压，虚拟位线被设定为接地电压，然后使一对位线和虚拟位线相等。 当在随后的读取操作中激活字线时，一对位线处于低于电源电压的中间电位，使得存取晶体管的视在电流驱动能力降低，并且存储单元的静态噪声容限 增加
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公开(公告)号：US07301793B2
公开(公告)日：2007-11-27
申请号：US10879753
申请日：2004-06-30
CPC分类号： G11C7/1069 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C11/419 , G11C2207/002
摘要： A semiconductor memory device comprises a plurality of memory cell groups. Each memory cell group includes at least two memory cells. Each memory cell group includes a read section and a write section. The data of a memory cell is read from one bit line to a read global bit line through the read section. The write section is shared by at least two memory cells in the same memory cell group. Thus, writing of data in a memory cell is desirably achieved although the memory cell has a common 6-transistor structure.
摘要翻译： 半导体存储器件包括多个存储单元组。 每个存储单元组包括至少两个存储单元。 每个存储单元组包括读取部分和写入部分。 存储单元的数据通过读取部分从一个位线读取到读出的全局位线。 写入部分由相同存储器单元组中的至少两个存储器单元共享。 因此，尽管存储单元具有共同的6晶体管结构，但期望地将数据写入存储单元。
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公开(公告)号：US20050207212A1
公开(公告)日：2005-09-22
申请号：US11075740
申请日：2005-03-10
IPC分类号： G11C11/41 , G11C11/24 , G11C11/413
CPC分类号： G11C11/413
摘要： An SRAM includes: a memory cell array; and a control circuit. Each memory cell includes: inverters; and access transistors interposed in lines connecting internal nodes in the respective inverters and a pair of bit lines BIT and NBIT. The control circuit includes a bias circuit for transmitting signals to the bit lines BIT and NBIT. A memory cell power supply terminal and a control circuit power supply terminal are isolated from each other. When power is turned on, the bias circuit sets one of the bit lines at a power supply potential (high potential) and the other bit line at a ground potential, so that a minute potential difference is generated between the internal nodes and thereby data is initialized. Transistors in the memory cell do not need to be asymmetric.
摘要翻译： SRAM包括：存储单元阵列; 和控制电路。 每个存储单元包括：逆变器; 以及插入在连接各个反相器中的内部节点的线路中的存取晶体管和一对位线BIT和NBIT。 控制电路包括用于向位线BIT和NBIT发送信号的偏置电路。 存储单元电源端子和控制电路电源端子彼此隔离。 当电源接通时，偏置电路将位线之一置于电源电位（高电位），另一位线处于接地电位，从而在内部节点之间产生微小的电位差，从而数据为 初始化 存储单元中的晶体管不需要是不对称的。
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7.发明授权公开(公告)号：US07277342B2
公开(公告)日：2007-10-02
申请号：US11480911
申请日：2006-07-06
IPC分类号： G11C7/02
摘要： Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to environmental factors, such as the temperature condition, voltage condition, etc. The timing of reading data from memory cells is controlled according to a change in voltage of the dummy read line DRD which is caused due to the discharge of the precharged dummy read line DRD.
摘要翻译： 提供了根据存储信息改变虚拟读取线DRD的负载电容的复位虚拟单元。 根据诸如温度条件，电压条件等的环境因素将存储器信息设置到复位虚拟单元。根据引起的虚拟读取线DRD的电压变化来控制从存储器单元读取数据的定时 由于预充电虚拟读取线DRD的放电。
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公开(公告)号：US07136297B2
公开(公告)日：2006-11-14
申请号：US11075740
申请日：2005-03-10
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： An SRAM includes: a memory cell array; and a control circuit. Each memory cell includes: inverters; and access transistors interposed in lines connecting internal nodes in the respective inverters and a pair of bit lines BIT and NBIT. The control circuit includes a bias circuit for transmitting signals to the bit lines BIT and NBIT. A memory cell power supply terminal and a control circuit power supply terminal are isolated from each other. When power is turned on, the bias circuit sets one of the bit lines at a power supply potential (high potential) and the other bit line at a ground potential, so that a minute potential difference is generated between the internal nodes and thereby data is initialized. Transistors in the memory cell do not need to be asymmetric.
摘要翻译： SRAM包括：存储单元阵列; 和控制电路。 每个存储单元包括：逆变器; 以及插入在连接各个反相器中的内部节点的线路中的存取晶体管和一对位线BIT和NBIT。 控制电路包括用于向位线BIT和NBIT发送信号的偏置电路。 存储单元电源端子和控制电路电源端子彼此隔离。 当电源接通时，偏置电路将位线之一置于电源电位（高电位），另一位线处于接地电位，从而在内部节点之间产生微小的电位差，从而数据为 初始化 存储单元中的晶体管不需要是不对称的。
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公开(公告)号：US20070019485A1
公开(公告)日：2007-01-25
申请号：US11480911
申请日：2006-07-06
摘要： Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to environmental factors, such as the temperature condition, voltage condition, etc. The timing of reading data from memory cells is controlled according to a change in voltage of the dummy read line DRD which is caused due to the discharge of the precharged dummy read line DRD.
摘要翻译： 提供了根据存储信息改变虚拟读取线DRD的负载电容的复位虚拟单元。 根据诸如温度条件，电压条件等的环境因素将存储器信息设置到复位虚拟单元。根据引起的虚拟读取线DRD的电压变化来控制从存储器单元读取数据的定时 由于预充电虚拟读取线DRD的放电。
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公开(公告)号：US07054211B2
公开(公告)日：2006-05-30
申请号：US10732297
申请日：2003-12-11
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C7/12 , G11C7/14 , G11C2207/065
摘要： A semiconductor memory storage is disclosed, in which the gate of each of a plurality of n-channel transistors is connected to the corresponding one of a plurality of word lines on the output side of each word line driver. The source of the n-channel transistor is connected through a selective switching element to the gate of the corresponding one of a plurality of replica transistors connected to a dummy bit line. The gate of each replica transistor is connected to the corresponding one of discharge transistors. The dummy bit line is connected to a sense amplifier through a logic gate.
摘要翻译： 公开了一种半导体存储器存储器，其中多个n沟道晶体管中的每一个的栅极连接到每个字线驱动器的输出侧上的多个字线中的相应一个字线。 n沟道晶体管的源极通过选择性开关元件连接到连接到虚拟位线的多个复制晶体管中的对应的一个的栅极。 每个复制晶体管的栅极连接到相应的一个放电晶体管。 虚拟位线通过逻辑门连接到读出放大器。
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