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公开(公告)号：US07697320B2
公开(公告)日：2010-04-13
申请号：US12122174
申请日：2008-05-16
IPC分类号： G11C11/40
CPC分类号： G11C11/412 , G11C11/419
摘要： In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided.
摘要翻译： 在具有第一和第二负载晶体管，第一和第二驱动晶体管以及第一和第二存取晶体管的存储单元中，设置在第一位线和第一存储器节点之间并具有栅极端子的第三存取晶体管 连接到第一列线和设置在第二位线和第二存储器节点之间并且具有连接到第二列线的栅极端子的第四存取晶体管。
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公开(公告)号：US20090016144A1
公开(公告)日：2009-01-15
申请号：US12122174
申请日：2008-05-16
IPC分类号： G11C8/08
CPC分类号： G11C11/412 , G11C11/419
摘要： In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided.
摘要翻译： 在具有第一和第二负载晶体管，第一和第二驱动晶体管以及第一和第二存取晶体管的存储单元中，设置在第一位线和第一存储器节点之间并具有栅极端子的第三存取晶体管 连接到第一列线和设置在第二位线和第二存储器节点之间并且具有连接到第二列线的栅极端子的第四存取晶体管。
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公开(公告)号：US07885124B2
公开(公告)日：2011-02-08
申请号：US12203431
申请日：2008-09-03
申请人： Tsuyoshi Koike , Yuichirou Ikeda , Akira Masuo
发明人： Tsuyoshi Koike , Yuichirou Ikeda , Akira Masuo
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C5/147 , G11C11/413
摘要： A precharge circuit steps up a voltage of a bit line connected to a memory cell to a power supply voltage. A plurality of step-down circuits step down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the memory cell. The plurality of step-down circuits are connected to the bit line, and the plurality of step-down circuits are controlled by step-down control signals different to each other.
摘要翻译： 预充电电路将连接到存储单元的位线的电压升高到电源电压。 多个降压电路在从存储器单元读取数据之前，将位线的电压降低到低于电源电压的电压电平。 多个降压电路连接到位线，并且多个降压电路由彼此不同的降压控制信号控制。
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公开(公告)号：US20090067265A1
公开(公告)日：2009-03-12
申请号：US12203431
申请日：2008-09-03
申请人： Tsuyoshi Koike , Yuichirou Ikeda , Akira Masuo
发明人： Tsuyoshi Koike , Yuichirou Ikeda , Akira Masuo
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C5/147 , G11C11/413
摘要： A precharge circuit steps up a voltage of a bit line connected to a memory cell to a power supply voltage. A plurality of step-down circuits step down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the memory cell. The plurality of step-down circuits are connected to the bit line, and the plurality of step-down circuits are controlled by step-down control signals different to each other.
摘要翻译： 预充电电路将连接到存储单元的位线的电压升高到电源电压。 多个降压电路在从存储器单元读取数据之前，将位线的电压降低到低于电源电压的电压电平。 多个降压电路连接到位线，并且多个降压电路由彼此不同的降压控制信号控制。
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公开(公告)号：US20110316553A1
公开(公告)日：2011-12-29
申请号：US13189960
申请日：2011-07-25
IPC分类号： G01R31/00
CPC分类号： B60L11/182 , B60L3/00 , B60L2270/36 , Y02T10/7005 , Y02T10/7072 , Y02T10/7088 , Y02T90/122 , Y02T90/14
摘要： The abnormality detection system is provided for detecting an abnormality of an object. The abnormality detection system includes a high-frequency power source, a primary coil, a secondary coil and a controller. The high-frequency power source supplies power. The primary coil receives the power supplied from the high-frequency power source. The secondary coil is mounted to the object in noncontact with the primary coil for receiving power supplied from the primary coil. The controller is operable to detect the power received by the secondary coil and also to determine whether or not an abnormality is present in the object based on the detected power.
摘要翻译： 异常检测系统用于检测物体的异常。 异常检测系统包括高频电源，初级线圈，次级线圈和控制器。 高频电源供电。 初级线圈接收从高频电源提供的电力。 次级线圈以与初级线圈非接触的方式安装到物体上，用于接收从初级线圈提供的功率。 控制器可操作以检测由次级线圈接收的功率，并且还基于检测到的功率来确定对象中是否存在异常。
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公开(公告)号：US07817486B2
公开(公告)日：2010-10-19
申请号：US12267275
申请日：2008-11-07
申请人： Tsuyoshi Koike
发明人： Tsuyoshi Koike
IPC分类号： G11C11/416
CPC分类号： G11C11/419
摘要： A bit line potential monitor circuit is provided in a bit line, and a step-down circuit of the bit line is controlled base on information from the monitor circuit. As a result, the bit line is easily stepped down to an optimal potential level in accordance with a potential and a load capacity thereof without being affected by variability in devices or operation conditions.
摘要翻译： 在位线中提供位线电位监视电路，并且基于来自监视器电路的信息来控制位线的降压电路。 结果，根据其电位和负载能力，位线容易地降低到最佳电位电平，而不受设备或操作条件的变化的影响。
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公开(公告)号：US06075219A
公开(公告)日：2000-06-13
申请号：US893158
申请日：1997-07-15
CPC分类号： B23K11/318
摘要： In order to carry out quick and easy changeover of platens of an electrode unit, a shank holder connects a fixed lower electrode with a platen. Further, a movable upper electrode is connected with another platen by the shank, which is held by the shank holder. The shank holder and the shank are integrally connected with each other, and are positioned in such a manner that the electrodes can perform resistance welding. Merely detaching the shank and shank holder from their respective platens allows the desired electrode units to be mounted on, or removed from, a resistance welder without making any position adjustments of the electrodes. Consequently, adjustment of the positions of the electrodes becomes unnecessary, thereby facilitating quicker and easier changeover of electrodes.
摘要翻译： 为了实现对电极单元的压板的快速和容易的切换，柄座将固定的下电极与压板连接。 此外，可动上电极通过由柄支架保持的柄部与另一个压板连接。 柄支架和柄部彼此一体地连接，并且以这样的方式定位，使得电极可以执行电阻焊接。 仅将柄和柄固定器从它们各自的压板上分离，可使所需的电极单元安装在电阻焊机上或从电阻焊机上移除，而不对电极进行任何位置调节。 因此，不需要调节电极的位置，从而有助于更快速和更容易地切换电极。
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公开(公告)号：US08451654B2
公开(公告)日：2013-05-28
申请号：US13251596
申请日：2011-10-03
申请人： Tsuyoshi Koike
发明人： Tsuyoshi Koike
IPC分类号： G11C11/00
CPC分类号： H01L27/0207 , G11C11/412 , G11C15/04 , G11C15/046 , G11C17/12 , H01L27/1104
摘要： In two inverters included in a latch in a memory cell, the source or drain of a PMOS load transistor connected to a memory node is cut off, and the source or drain of an NMOS drive transistor connected to another memory node is cut off, whereby internal data is fixed or permanently stored in the memory cell while ensuring a resistance to damage to the gate of the transistor and without impairing the regularity of the layout.
摘要翻译： 在包括在存储单元中的锁存器中的两个反相器中，连接到存储器节点的PMOS负载晶体管的源极或漏极被切断，并且连接到另一存储器节点的NMOS驱动晶体管的源极或漏极被切断，由此 内部数据固定或永久地存储在存储单元中，同时确保对晶体管的栅极的损坏的抵抗力并且不损害布局的规则性。
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公开(公告)号：US20060013404A1
公开(公告)日：2006-01-19
申请号：US10524792
申请日：2003-08-21
申请人： Tsuyoshi Koike , Hiroshi Miyagi
发明人： Tsuyoshi Koike , Hiroshi Miyagi
IPC分类号： H04H5/00
CPC分类号： H04H40/72 , H04B1/1676
摘要： A stereo demodulator circuit comprising at least one noise control unit for performing a noise control responding to an RSSI (reception electric-field intensity) when the RSSI is within a specified range, further comprises an AD converter unit for AD-converting a signal corresponding to the RSSI and a control signal producing unit for producing a control signal for a noise control performed in the noise control unit according to a noise level when the noise level obtained by the AD conversion is within the above described specified range. The control signal producing unit comprises an offset unit for digitally offsetting a signal obtained through the above described AD conversion by a predefined value and truncating lower bits off the offset value by the number of bits in compliance with a grade of the noise control accuracy and outputs the control signal based on the signal obtained from the offset unit.
摘要翻译： 一种立体声解调器电路，包括至少一个噪声控制单元，用于当RSSI在指定范围内时响应于RSSI（接收电场强度）执行噪声控制，还包括AD转换单元，用于AD转换对应于 RSSI和控制信号产生单元，用于当通过AD转换获得的噪声电平在上述指定范围内时，根据噪声电平产生用于在噪声控制单元中执行的噪声控制的控制信号。 控制信号产生单元包括：偏移单元，用于通过预定义的值将通过上述AD转换获得的信号数字偏移，并根据噪声控制精度等级将偏移值的低位截断位数 基于从偏移单元获得的信号的控制信号。
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公开(公告)号：US06671219B1
公开(公告)日：2003-12-30
申请号：US09979951
申请日：2001-11-27
IPC分类号： G11C800
CPC分类号： G11C7/1012 , G06F12/02 , G11C7/06 , G11C7/1006 , G11C7/1015
摘要： In a storage device from which n bits of data are read at a time, data pieces whose logical bit positions are 0*8+k, 1*8+k, 2*8+k, 3*8+k, . . . , m*8+k (where k and m are natural numbers satisfying 0≦k≦7, 0 ≦m≦n/8−1) are stored in memory cells close to one another in a memory cell array, and the bit positions are shifted by a predetermined number of bits when data having a small number of significant bits is read from the memory cell array.
摘要翻译： 在一次从其读取n位数据的存储装置中，其逻辑位位置为0 * 8 + k，1 * 8 + k，2 * 8 + k，3 * 8 + k， 。 。 ，m * 8 + k（其中k和m是满足0 <= k <= 7,0 <= m <= n / 8-1的自然数）被存储在存储单元阵列中彼此靠近的存储单元中， 并且当从存储单元阵列读取具有少量有效位的数据时，位位置偏移预定位数。
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