公开(公告)号：US20060002954A1

公开(公告)日：2006-01-05

申请号：US11155682

申请日：2005-06-20

申请人： Akira Tabata ,  Takumi Nakamura

发明人： Akira Tabata ,  Takumi Nakamura

IPC分类号： A61K35/84 ,  A61K35/78

CPC分类号： A61K45/06 ,  A61K36/062 ,  A61K36/48 ,  A61K36/899 ,  A61K36/8994 ,  A61K2236/19 ,  A61K2300/00

摘要： The object of the present invention is to provide a composition which is capable of going into erythrocyte or into cells, trapping not only oxygen radicals but also hydroxyl radicals, and preventing or improving various symptoms including hypertension, excessive sensitivity to cold, diabetes, Parkinson's disease, menstrual disorder, brain infarct, atopic dermatitis, hay fever, articular rheumatism, autonomic ataxia, and the like by oral intake. The present invention relates to an invention of a composition trapping radicals in organism comprising the steps of: roasting soy bean, wheat germ, adlay, husked rice germ, and rice bran, which are materials at a temperature of 50 to 150° C. independently, followed by steaming them independently, and fermenting them independently with each of said materials by adding at least one species of edible microbes selected from microbes belonging to Aspergilius oryzae, and after fermentation, adding fine powders of at least green tea powders, sesame, rosemary, acerola, yuzu, carrot, Gymnema Sylvestre and green barley to each of said materials thereafter mixing, further followed by making the mixture ultra fine powders with 30 to 50 μm.

摘要翻译： 本发明的目的是提供能够进入红细胞或细胞的组合物，不仅捕获氧自由基而且捕获羟基，并且预防或改善各种症状，包括高血压，对感冒的过度敏感性，糖尿病，帕金森病 月经紊乱，脑梗死，特应性皮炎，花粉症，关节风湿病，自主性共济失调等。 本发明涉及一种在生物体中捕获自由基的组合物的发明，其包括以下步骤：独立地焙烧大豆，小麦胚芽，阿德莱，脱壳米胚芽和米糠，它们是温度在50至150℃的材料 ，然后独立地蒸煮，并通过加入至少一种选自属于米曲霉的微生物的食用微生物，每种所述材料进行发酵，发酵后加入至少绿茶粉末，芝麻，迷迭香的细粉 ，槭树，柚子，胡萝卜，Gymnema Sylvestre和绿色大麦，然后混合，然后混合超细粉末30-50um。

公开(公告)号：US4824794A

公开(公告)日：1989-04-25

申请号：US170618

申请日：1988-03-14

申请人： Akira Tabata ,  Motoshu Miyajima ,  Kazushi Kawaguchi

发明人： Akira Tabata ,  Motoshu Miyajima ,  Kazushi Kawaguchi

IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/66287 ,  H01L21/28525 ,  H01L29/66272 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/117

摘要： A bipolar transistor having self-aligned base and emitter regions is fabricated in a silicon layer which is epitaxially grown on a substrate so as to fill up a cavity formed through a polysilicon layer deposited on the substrate. The polysilicon layer is doped with impurities for creating an extrinsic base region in the epitaxially grown silicon layer and is insulated from the emitter electrode by a dielectric layer formed thereon. The dielectric layer can be provided by selectively oxidizing the polysilicon layer. Thus, the step formed at the emitter electrode is small and equal to the thickness of the dielectric layer, about 3000 .ANG., for example, thereby eliminating the faulty step coverage in the prior art self-aligned bipolar transistor usually having the step as large as 1 micron.

摘要翻译： 具有自对准基极和发射极区域的双极晶体管制造在硅衬底上外延生长以填充通过沉积在衬底上的多晶硅层形成的腔的硅层。 多晶硅层掺杂有用于在外延生长的硅层中产生非本征基区的杂质，并且通过其上形成的电介质层与发射极绝缘。 可以通过选择性地氧化多晶硅层来提供电介质层。 因此，例如在发射电极处形成的台阶小，等于介电层的厚度，例如约为3000，从而消除了现有技术的自对准双极晶体管的故障台阶覆盖，通常具有如 1微米。

公开(公告)号：US4579625A

公开(公告)日：1986-04-01

申请号：US652075

申请日：1984-09-19

申请人： Akira Tabata ,  Motoshu Miyajima ,  Yoshifumi Kikuchi

发明人： Akira Tabata ,  Motoshu Miyajima ,  Yoshifumi Kikuchi

IPC分类号： H01L27/082 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8228 ,  H01L21/8238 ,  H01L27/06 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/82285 ,  H01L21/76 ,  H01L21/76297 ,  H01L21/823878 ,  Y10S438/928 ,  Y10S438/969

摘要： A method of producing a complementary semiconductor device having p-type islands and n-type islands in a dielectric isolation structure, including removing a projecting portion of a polycrystalline silicon layer, which is formed at the same time as the formation of an epitaxial silicon layer for one of two types of islands, so as to obtain an almost smooth exposed surface. The smooth surface contributes to the formation of a good masking pattern on the epitaxial silicon layer by a photoetching method, so that mesa portions for islands having exact dimensions are formed at predetermined positions.

摘要翻译： 一种在电介质隔离结构中制造具有p型岛和n型岛的互补半导体器件的方法，包括去除与形成外延硅层同时形成的多晶硅层的突出部分 对于两种类型的岛之一，以获得几乎平滑的暴露表面。 光滑表面有助于通过光刻方法在外延硅层上形成良好的掩模图案，使得具有精确尺寸的岛的台面部分形成在预定位置。

公开(公告)号：USRE34400E

公开(公告)日：1993-10-05

申请号：US582000

申请日：1990-09-14

申请人： Hiroshi Goto ,  Akira Tabata

发明人： Hiroshi Goto ,  Akira Tabata

IPC分类号： H01L21/763 ,  H01L21/302 ,  H01L21/76

CPC分类号： H01L21/763

摘要： A method for fabricating an isolation region in a semiconductor substrate that produces neither a "bird's beak" nor a "bird's head". A smooth substrate surface is provided, which is preferable for multi-layered wiring. The packing density of devices in a bipolar IC circuit can be increased. A sharp-edged isolation groove having a U-shaped cross-section is made by reactive ion etching. The inner surface of the isolation groove is coated by an insulating film. Then the groove is buried with polycrystalline semiconductor material. The polycrystalline material which is deposited on the surface of the substrate is etched off. At the same time the polycrystalline material in the groove is also etched to a specific depth from the surface. An insulating film is then deposited so as to again fill the groove. Then the substrate surface is polished or etched to provide a flat surface.

公开(公告)号：US4567646A

公开(公告)日：1986-02-04

申请号：US676988

申请日：1984-11-30

申请人： Tamotsu Ishikawa ,  Hirokazu Tanaka ,  Akira Tabata

发明人： Tamotsu Ishikawa ,  Hirokazu Tanaka ,  Akira Tabata

IPC分类号： H01L21/762 ,  H01L21/302 ,  H01L21/76

CPC分类号： H01L21/76297 ,  Y10S148/026 ,  Y10S148/085 ,  Y10S148/122 ,  Y10S438/969 ,  Y10S438/977

摘要： A method for fabricating a wafer for a dielectric isolation (DI) integrated circuit device is provided, wherein the substrate of the wafer, comprises portions of polycrystalline silicon positioned beneath regions for electrical elements, namely, "islands", and portions of single crystal silicon are positioned in other areas of the wafer such as scribing regions, peripheral regions and contact regions. The single crystal portions of the substrate are grown during its fabricating steps by exposing surfaces of an original substrate of single crystal silicon, before the deposition of silicon onto the original substrate, by removing a dielectric isolation layer over the predetermined regions to be exposed. The single crystal silicon portions of the wafer provide various advantages for subsequent mechanical processing of the wafer such as shaping and rounding of the peripheral region and the scribing of the wafer into dice.

摘要翻译： 提供一种用于制造用于电介质隔离（DI）集成电路器件的晶片的方法，其中晶片的衬底包括位于用于电气元件的区域下方的多晶硅部分，即“岛”，以及部分单晶硅 位于晶片的其他区域，例如划线区域，周边区域和接触区域。 在其制造步骤期间，通过在将硅沉积到原始衬底上之前暴露单晶硅的原始衬底的表面，通过在要暴露的预定区域上去除介电隔离层，使衬底的单晶部分生长。 晶片的单晶硅部分为晶片的随后的机械处理提供了各种优点，例如周边区域的成形和舍入以及将晶片划片成骰子。

公开(公告)号：US4509249A

公开(公告)日：1985-04-09

申请号：US535342

申请日：1983-09-23

申请人： Hiroshi Goto ,  Akira Tabata

发明人： Hiroshi Goto ,  Akira Tabata

IPC分类号： H01L21/31 ,  H01L21/76 ,  H01L21/763 ,  H01L21/205

CPC分类号： H01L21/763 ,  H01L21/76

摘要： A method for fabricating an isolation region in a semiconductor substrate that produces neither a "bird's beak" nor a "bird's head". A smooth substrate surface is provided, which is preferable for multi-layered wiring. The packing density of devices in a bipolar IC circuit can be increased. A sharp-edged isolation groove having a U-shaped cross-section is made by reactive ion etching. The inner surface of the isolation groove is coated by an insulating film. Then the groove is buried with polycrystalline semiconductor material. The polycrystalline material which is deposited on the surface of the substrate is etched off. At the same time the polycrystalline material in the groove is also etched to a specific depth from the surface. An insulating film is then deposited so as to again fill the groove. Then the substrate surface is polished or etched to provide a flat surface.

摘要翻译： 一种制造半导体衬底中既不产生“鸟喙”也不产生“鸟头”的隔离区域的方法。 提供光滑的基板表面，这对于多层布线是优选的。 可以增加双极IC电路中器件的封装密度。 通过反应离子蚀刻制成具有U形横截面的尖锐的隔离槽。 隔离槽的内表面被绝缘膜包覆。 然后将沟槽埋入多晶半导体材料中。 蚀刻掉沉积在基板表面上的多晶材料。 同时，凹槽中的多晶材料也被蚀刻到表面的特定深度。 然后沉积绝缘膜以再次填充凹槽。 然后抛光或蚀刻衬底表面以提供平坦的表面。