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公开(公告)号：US07873856B2
公开(公告)日：2011-01-18
申请号：US11967389
申请日：2007-12-31
申请人： Alan L. Westwick , Dazhi Wei , Xiaoling Guo , Jia-Hau Liu
发明人： Alan L. Westwick , Dazhi Wei , Xiaoling Guo , Jia-Hau Liu
CPC分类号： H03K17/22 , H03K17/223
摘要： The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. Monitoring circuitry determines if a chip supply voltage level exceeds a threshold level necessary to maintain operation of the digital circuitry.
摘要翻译： 单片微控制器单元包括具有正常功率操作模式和低功率操作模式的处理单元。 模拟电路和数字电路连接到处理单元。 监控电路确定芯片电源电压电平是否超过维持数字电路运行所需的阈值电平。
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公开(公告)号：US07873854B2
公开(公告)日：2011-01-18
申请号：US11865654
申请日：2007-10-01
申请人： Alan L. Westwick , Dazhi Wei , Xiaoling Guo , Jia-Hau Liu
发明人： Alan L. Westwick , Dazhi Wei , Xiaoling Guo , Jia-Hau Liu
IPC分类号： G06F1/00
CPC分类号： H03K17/22 , H03K17/223
摘要： The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. A power management unit controls power operations of the processing unit, the analog circuitry and the digital circuitry. Power monitoring circuitry provides power control signals to the power management unit. The power monitoring circuitry further includes a system voltage monitoring circuit for generating a system voltage control signal responsive to a system voltage level with respect to a predetermined level. The power monitoring circuitry also includes a supply monitoring circuit for determining if a chip supply voltage level exceeds a threshold level.
摘要翻译： 单片微控制器单元包括具有正常功率操作模式和低功率操作模式的处理单元。 模拟电路和数字电路连接到处理单元。 电源管理单元控制处理单元，模拟电路和数字电路的功率操作。 电源监控电路向电源管理单元提供电源控制信号。 功率监测电路还包括系统电压监测电路，用于响应于相对于预定电平的系统电压电平来产生系统电压控制信号。 功率监视电路还包括用于确定芯片电源电压电平是否超过阈值电平的电源监控电路。
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公开(公告)号：US07908500B2
公开(公告)日：2011-03-15
申请号：US11865661
申请日：2007-10-01
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors.
摘要翻译： 微控制器包括具有处理单元的处理单元，该处理单元具有正常的功率操作模式和低功率操作模式。 处理单元还具有连接到处理单元的数字电路，其具有与其相关联的多个逻辑电路以处理数字值。 当处理单元进入低功率操作模式时，多个保持触发器与数字电路相关联，用于存储数字电路内的至少一个或多个逻辑电路的逻辑状态。 多个保持触发器包括用于在低功率和高功率工作模式下操作的第一类型的晶体管，以及用于仅在正常操作模式下操作的第二类型的晶体管，并且其中基本上在其中的数字电路的其余部分 处理单元包括第二类型的晶体管。
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4.发明授权公开(公告)号：US07852061B2
公开(公告)日：2010-12-14
申请号：US11865648
申请日：2007-10-01
IPC分类号： G05F3/16
CPC分类号： G05F3/30 , H02M2001/0032 , Y02B70/16 , Y10S323/907
摘要： An apparatus comprises a band gap voltage generator circuit for generating a band gap voltage. A temperature invariant current generator is located within the band gap voltage generator circuit for generating a temperature invariant current. A temperature invariant current correction circuit is located within the band gap voltage generator circuit and adjusts the output voltage responsive to the temperature invariant current without altering temperature characteristics of the temperature invariant current.
摘要翻译： 一种装置包括用于产生带隙电压的带隙电压发生器电路。 温度不变电流发生器位于带隙电压发生器电路内，用于产生温度不变电流。 温度不变电流校正电路位于带隙电压发生器电路内，并根据温度不变电流调节输出电压，而不改变温度不变电流的温度特性。
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公开(公告)号：US20130221940A1
公开(公告)日：2013-08-29
申请号：US13404558
申请日：2012-02-24
申请人： Shouli Yan , Dazhi Wei , Alan L. Westwick
发明人： Shouli Yan , Dazhi Wei , Alan L. Westwick
IPC分类号： G05F1/10
CPC分类号： G05F1/565
摘要： A technique includes using a pass device of a linear regulator to provide an output signal for the linear regulator in response to a signal that is received at a control terminal of the pass device. The control terminal is coupled to a node, and the node is associated with a bias current. The technique includes using a feedback path to communicate a feedback current with the node to regulate the output signal. The use of the feedback path includes regulating a magnitude of the feedback current to be within a range of magnitudes, which include a magnitude that exceeds a magnitude of the bias current.
摘要翻译： 一种技术包括使用线性调节器的通过装置来响应于在通过装置的控制端子处接收到的信号来为线性调节器提供输出信号。 控制终端耦合到节点，节点与偏置电流相关联。 该技术包括使用反馈路径将反馈电流与节点通信以调节输出信号。 反馈路径的使用包括将反馈电流的幅度调节在包括超过偏置电流的幅度的幅度的幅度范围内。
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6.发明授权System and method for calibrating bias current for low power RTC oscillator 有权用于校准低功耗RTC振荡器的偏置电流的系统和方法公开(公告)号：US07714674B2
公开(公告)日：2010-05-11
申请号：US11967372
申请日：2007-12-31
申请人： Xiaoling Guo , Alan L. Westwick
发明人： Xiaoling Guo , Alan L. Westwick
IPC分类号： H03L1/00
CPC分类号： H03L1/02
摘要： The integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A real time clock circuit provides a system clock for the processing core. The real time clock further comprises an internal oscillator that generates the system clock for the integrated circuit package. The internal oscillator has a factory calibrated bias current. An internal oscillator control register controls the operation of the internal oscillator responsive to control bits of the programmable load capacitor array controlled by the processing core.
摘要翻译： 集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。 实时时钟电路为处理核心提供系统时钟。 实时时钟还包括产生用于集成电路封装的系统时钟的内部振荡器。 内部振荡器具有出厂校准的偏置电流。 响应于由处理核心控制的可编程负载电容阵列的控制位，内部振荡器控制寄存器控制内部振荡器的操作。
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公开(公告)号：US07768242B2
公开(公告)日：2010-08-03
申请号：US11865645
申请日：2007-10-01
申请人： Dazhi Wei , Alan L. Westwick
发明人： Dazhi Wei , Alan L. Westwick
CPC分类号： H02M3/156 , H02M2001/0009
摘要： A DC to DC boost converter circuit receives a DC input voltage and converts it to a DC output voltage at a different voltage level than the DC input voltage. The DC to DC boost converter includes a switching power converter for receiving the input voltage on an input and converting the input voltage to an output as the DC output voltage in response to pulse control signals. A switching controller generates the pulse control signals during a switching cycle. Current sensing circuitry limits a current passing through the switching power converter. The current sensing circuitry generates an overload signal when the current exceeds a reference value. The current sensing circuitry sensing the current with a current sensing resistor having a size of at least approximately 500 ohms.
摘要翻译： DC-DC升压转换器电路接收DC输入电压并将其转换成与DC输入电压不同的电压电平的DC输出电压。 DC-DC升压转换器包括用于接收输入端的输入电压的开关电源转换器，并且响应于脉冲控制信号将输入电压转换为作为DC输出电压的输出。 开关控制器在开关周期内产生脉冲控制信号。 电流检测电路限制了通过开关电源转换器的电流。 当电流超过参考值时，电流检测电路产生过载信号。 电流感测电路用具有至少约500欧姆的尺寸的电流感测电阻感测电流。
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公开(公告)号：US07802113B2
公开(公告)日：2010-09-21
申请号：US11618433
申请日：2006-12-29
申请人： Alan L. Westwick , Ka Y. Leung
发明人： Alan L. Westwick , Ka Y. Leung
IPC分类号： G06F1/26
CPC分类号： H02M3/156
摘要： An integrated system on a chip includes processing circuitry that performs predefined digital processing functions on the chip. The processing circuitry operates responsive to a regulated voltage. An on-chip boost converter generates the regulated voltage responsive to an off-chip voltage provided by an off chip voltage source. The regulated voltage source has a voltage level greater than the off-chip voltage.
摘要翻译： 芯片上的集成系统包括在芯片上执行预定义的数字处理功能的处理电路。 处理电路响应于调节电压而工作。 片上升压转换器响应于由片外电压源提供的片外电压产生调节电压。 调节电压源具有大于片外电压的电压电平。
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9.发明授权Method and apparatus for a data converter with a single operational amplifier 失效具有单个运算放大器的数据转换器的方法和装置
公开(公告)号：US5633640A
公开(公告)日：1997-05-27
申请号：US349592
申请日：1994-12-05
申请人： Todd L. Barker , Alan L. Westwick
发明人： Todd L. Barker , Alan L. Westwick
摘要： A data converter (10) includes an analog input element (12), an operational amplifier (14), a first reference input element (18), a second reference input element (22), and a control element (34). The analog input element (12) operably couples the analog signal to a first input (13) of the operational amplifier (14). The first and second reference input elements (18 & 22) respectively couple a first signal (16) and a second signal (22) to a first input of the operational amplifier (14). The control element (34) generates the control signal based on an output of the operational amplifier (14) to force the first input node (13) to be equivalent to the second input node (15) of the operational amplifier (14). The data converter (10) also includes an analog-to-digital converter (26) that allows the circuit to perform a sigma-delta conversion.
摘要翻译： 数据转换器（10）包括模拟输入元件（12），运算放大器（14），第一参考输入元件（18），第二参考输入元件（22）和控制元件（34）。 模拟输入元件（12）可操作地将模拟信号耦合到运算放大器（14）的第一输入端（13）。 第一和第二参考输入元件（18和22）分别将第一信号（16）和第二信号（22）耦合到运算放大器（14）的第一输入端。 控制元件（34）基于运算放大器（14）的输出产生控制信号，以迫使第一输入节点（13）等效于运算放大器（14）的第二输入节点（15）。 数据转换器（10）还包括允许电路执行Σ-Δ转换的模拟 - 数字转换器（26）。
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公开(公告)号：US5160894A
公开(公告)日：1992-11-03
申请号：US822224
申请日：1992-01-17
申请人： Alan L. Westwick
发明人： Alan L. Westwick
摘要： A frequency synthesizer circuit (10). Circuit (10) has a counter (12), a latch/decoder (14), a divider (16), and an optional wave shaper (18) which synthesize an output clock signal X. Counter (12) counts a number of clock signal N periods that occur within one clock signal M period and this count is stored as a count value. The count value is latched and/or decoded by the latch/decoder (14) to produce a divisor which is output from the latch/decoder (14) to the divider (16). The divider (16) divides a clock signal N frequency by the divisor to provide a spiked waveform to the wave shaper (18). The wave shaper (18) alters a frequency and/or a duty cycle of the spiked waveform to produce the clock signal X. Clock signal X has a substantially constant frequency regardless of the clock signal N frequency or operational variation in the system clock N frequency.
摘要翻译： 频率合成器电路（10）。 电路（10）具有计数器（12），锁存/解码器（14），分频器（16）和可选的波形整形器（18），其合成输出时钟信号X.计数器（12）对多个时钟 在一个时钟信号M周期内发生信号N个周期，并且该计数被存储为计数值。 计数值被锁存/解码器（14）锁存和/或解码，以产生从锁存/解码器（14）输出到除法器（16）的除数。 分频器（16）将时钟信号N频率除以除数以向波形整形器（18）提供加标波形。 波形整形器（18）改变加标波形的频率和/或占空比以产生时钟信号X.时钟信号X具有基本恒定的频率，而不管时钟信号N的频率或系统时钟的频率N的频率 。
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