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1.发明授权公开(公告)号：US07233197B2
公开(公告)日：2007-06-19
申请号：US11006974
申请日：2004-12-07
IPC分类号： H01L25/00
CPC分类号： G06F17/505 , H03K19/0016
摘要： Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.
摘要翻译： 通过将电路放置在低泄漏待机模式下，避免电路元件（如晶体管）的漏电流。 这些电路被配置成使得在待机模式下避免跨漏电的电路部件的电压差。 使用各种手段来配置电路，例如配置端口，数据输入线，扫描链等。在包含可重新配置的设备的实施例中，使用低阈值晶体管来实现路由网络。
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公开(公告)号：US06946903B2
公开(公告)日：2005-09-20
申请号：US10628906
申请日：2003-07-28
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H03K19/00 , H01L25/00
CPC分类号： G06F17/505 , H03K19/0016
摘要： Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.
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3.发明授权公开(公告)号：US07315201B2
公开(公告)日：2008-01-01
申请号：US11765273
申请日：2007-06-19
IPC分类号： H01L25/00
CPC分类号： G06F17/505 , H03K19/0016
摘要： Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.
摘要翻译： 通过将电路放置在低泄漏待机模式下，避免电路元件（如晶体管）的漏电流。 这些电路被配置成使得在待机模式下避免跨漏电的电路部件的电压差。 使用各种手段来配置电路，例如配置端口，数据输入线，扫描链等。在包含可重新配置的设备的实施例中，使用低阈值晶体管来实现路由网络。
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公开(公告)号：US07461234B2
公开(公告)日：2008-12-02
申请号：US11130613
申请日：2005-05-16
IPC分类号： G06F15/00 , G06F15/163
CPC分类号： G06F9/3001 , G06F9/30181 , G06F9/3879 , G06F9/3897 , G06F15/7867 , H03K17/002 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing networks. The multiplexers are controlled by the ALUs in the same cluster, or alternatively by ALUs in other clusters, via a special purpose routing network. Components of applications configured onto the array are selectively implemented in either multiplexers or ALUs, as determined by the relative efficiency of implementing the component in one or the other type of processing element, and by the relative availability of the processing element types. Multiplexer control signals are generated from combinations of ALU status signals, and optionally routed to control multiplexers in different clusters.
摘要翻译： 异构阵列包括处理元件群。 集群包括通过直接连接和各种通用路由网络链接的ALU和多路复用器的组合。 多路复用器由同一集群中的ALU或其他集群中的ALU通过专用路由网络控制。 通过在一个或另一种类型的处理元件中实现组件的相对效率以及处理元件类型的相对可用性来确定，配置到阵列上的应用的组件被选择性地实现在多路复用器或ALU中。 多路复用器控制信号从ALU状态信号的组合产生，并且可选地路由到不同簇中的控制多路复用器。
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5.发明授权Memory device that functions as a content addressable memory or a random access memory 失效用作内容可寻址存储器或随机存取存储器的存储器件
公开(公告)号：US5408434A
公开(公告)日：1995-04-18
申请号：US190912
申请日：1994-02-03
IPC分类号： H01L21/82 , G11C15/04 , H03K19/177 , G11C8/00
CPC分类号： H03K19/17796 , G11C15/04 , H03K19/177 , H03K19/17704
摘要： A programmable logic device is disclosed which can be used either as a look-up table logic device or as a logic function generator. This enables combinations to be provided such as the combination of a look-up table with a fixed gate field programmable gate array.
摘要翻译： 公开了可用作查找表逻辑器件或逻辑函数发生器的可编程逻辑器件。 这使得可以提供组合，例如查找表与固定门现场可编程门阵列的组合。
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公开(公告)号：US5491703A
公开(公告)日：1996-02-13
申请号：US84566
申请日：1993-06-29
CPC分类号： G11C15/04
摘要： A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least one additional cell for storing a checking bit and a match line for providing a signal to indicate when a match occurs between an input data word and data stored in a row of cells, which method comprises storing in at least one row of cells a data word in data cells of the row and a checking bit in said at least one additonal cell of the row, the checking bit having a value dependent on the content of the data word in accordance with an error checking system, and controlling a memory accessing system to effect an associate operation by inputting to the columns of cells an input word with an input checking bit dependent on said input word in accordance with the same error checking system, comparing the input word and input checking bit with stored contents of each row of cells and in any row where a mismatch of the input data word with the stored data word occurs causing at least two cells in that row to change a signal level on a match line for that row, said memory accessing system being arranged to operate with a time delay for each associate operation which is less than that required for a single cell mismatch. The invention also provides a content addressable memory.
摘要翻译： 一种访问具有以行和列的阵列连接的多个RAM单元的内容可寻址存储器的方法，每行具有用于存储数据字的多个单元，用于存储检查位的至少一个附加单元和匹配线 用于提供信号以指示何时在输入数据字与存储在一行单元格中的数据之间发生匹配，该方法包括在至少一行单元中存储该行的数据单元中的数据字和所述行中的检查位 所述行的至少一个附加单元，所述检查位具有依赖于错误检查系统的取决于所述数据字的内容的值，以及通过输入到所述单元格列来控制存储器访问系统来执行关联操作 根据相同的错误检查系统，输入字与具有取决于所述输入字的输入检查位相比较，将输入字和输入检查位与每行单元格的存储内容进行比较，并在任何行w 这里，输入数据字与存储的数据字的不匹配发生，导致该行中的至少两个单元改变该行的匹配线上的信号电平，所述存储器访问系统被布置为以每个关联的时间延迟 小于单个单元不匹配所需的操作。 本发明还提供一种内容可寻址存储器。
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7.发明授权Programmable logic device with memory that can store routing data of logic data 失效具有可存储逻辑数据路由数据的可编程逻辑器件
公开(公告)号：US5473267A
公开(公告)日：1995-12-05
申请号：US383108
申请日：1995-02-03
IPC分类号： H01L21/82 , G11C15/04 , H03K19/177 , G06F7/38 , H03K19/173
CPC分类号： H03K19/17796 , G11C15/04 , H03K19/177 , H03K19/17704
摘要： A programmable logic device is disclosed which can be used either as a look-up table logic device or as a logic function generator. This enables combinations to be provided such as the combination of a look-up table with a fixed gate field programmable gate array.
摘要翻译： 公开了可用作查找表逻辑器件或逻辑函数发生器的可编程逻辑器件。 这使得可以提供组合，例如查找表与固定门现场可编程门阵列的组合。
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公开(公告)号：US07471643B2
公开(公告)日：2008-12-30
申请号：US10188388
申请日：2002-07-01
IPC分类号： H04L12/28
CPC分类号： G06F9/3001 , G06F9/3842 , G06F9/3885 , G06F9/3897 , G06F15/7867 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17796
摘要： A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing networks. The multiplexers are controlled by the ALUs in the same cluster, or alternatively by ALUs in other clusters, via a dedicated multiplexer control network. Components of applications configured onto the array are selectively implemented in either multiplexers or ALUs, as determined by the relative efficiency of implementing the component in one or the other type of processing element, and by the relative availability of the processing element types. Multiplexer control signals are generated from combinations of ALU status signals, and optionally routed to control multiplexers in different clusters.
摘要翻译： 异构阵列包括处理元件群。 集群包括通过直接连接和各种通用路由网络链接的ALU和多路复用器的组合。 多路复用器由同一集群中的ALU或其他集群中的ALU通过专用多路复用器控制网络来控制。 通过在一个或另一种类型的处理元件中实现组件的相对效率以及处理元件类型的相对可用性来确定，配置到阵列上的应用的组件被选择性地实现在多路复用器或ALU中。 多路复用器控制信号从ALU状态信号的组合产生，并且可选地路由到不同簇中的控制多路复用器。
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公开(公告)号：US06859084B2
公开(公告)日：2005-02-22
申请号：US10224093
申请日：2002-08-19
IPC分类号： H03K19/0948 , H03K19/00 , H03K19/0185 , H03K19/173 , H03K5/08
CPC分类号： H03K19/1733 , H03K19/0013 , H03K19/018585
摘要： Power supply voltages are selectively modulated to correspond with degraded input voltages to a logic device. Modulated power supply voltages are provided to transistors within the logic device, so that the degraded input voltages supplied to the transistors are sufficient to turn the transistors substantially on or off. Leakage currents are prevented thereby from flowing across the transistors.
摘要翻译： 选择性地调制电源电压以对应于逻辑器件的降级的输入电压。 将调制的电源电压提供给逻辑器件内的晶体管，使得提供给晶体管的恶化输入电压足以使晶体管基本上导通或截止。 防止泄漏电流流过晶体管。
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10.发明授权Cache memory system including a RAM for storing data and CAM cell arrays for storing virtual and physical addresses 失效高速缓冲存储器系统包括用于存储数据的RAM和用于存储虚拟和物理地址的CAM单元阵列
公开(公告)号：US5574875A
公开(公告)日：1996-11-12
申请号：US031241
申请日：1993-03-12
CPC分类号： G06F12/1063
摘要： A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each require address translation to identify a physical page in a main memory, a second CAM cell array (52) holding line or word in page addresses which remain the same for virtual and physical addresses, a physical address memory (53) for holding physical page addresses for the main memory corresponding to virtual page addresses in said first array (51), said first array (51) being connected both to said physical address memory (52) to access said physical address memory in response to a hit output from said first CAM cell array and to control circuitry (57) coupled between said first and second arrays (51,52) and the data RAM (50) to access the data RAM (50) in response to hit outputs from both said first and second CAM cell arrays (51,52).
摘要翻译： 用于虚拟寻址的完全关联高速缓冲存储器包括数据RAM（50），用于保持虚拟页地址的第一CAM单元阵列（51），每个都需要地址转换来标识主存储器中的物理页，第二CAM单元阵列 52）保持对于虚拟和物理地址保持相同的页面地址中的行或字，用于保存对应于所述第一阵列（51）中的虚拟页地址的主存储器的物理页地址的物理地址存储器（53），所述第一 阵列（51）被连接到所述物理地址存储器（52），以响应于来自所述第一CAM单元阵列的命中输出而访问所述物理地址存储器，以及耦合在所述第一和第二阵列之间的控制电路（57） 52）和数据RAM（50），以响应于来自所述第一和第二CAM单元阵列（51,52）的命中输出来访问数据RAM（50）。
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