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公开(公告)号：US08519772B2
公开(公告)日：2013-08-27
申请号：US13075652
申请日：2011-03-30
IPC分类号： H03K17/687
CPC分类号： H03K19/0016
摘要： Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.
摘要翻译： 在集成电路中实现交流电源门控的结构和方法。 半导体结构包括电源门控电路，其包括一组电源门开关和产生使能信号的交替使能发生器。 每个相应的一个功率门开关由使能信号中的相应一个使能。 交替发电机产生使能信号，使得第一使能电源门极开关在一组电源门开关之间交替。
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公开(公告)号：US20120249213A1
公开(公告)日：2012-10-04
申请号：US13075652
申请日：2011-03-30
CPC分类号： H03K19/0016
摘要： Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.
摘要翻译： 在集成电路中实现交流电源门控的结构和方法。 半导体结构包括电源门控电路，其包括一组电源门开关和产生使能信号的交替使能发生器。 每个相应的一个功率门开关由使能信号中的相应一个使能。 交替发电机产生使能信号，使得第一使能电源门极开关在一组电源门开关之间交替。
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公开(公告)号：US08643987B2
公开(公告)日：2014-02-04
申请号：US13464131
申请日：2012-05-04
申请人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
发明人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
CPC分类号： H02H9/046
摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.
摘要翻译： 本发明提供一种用于消除电流泄漏的静电放电（ESD）保护装置及相关方法。 在一个实施例中，ESD保护装置包括：用于接收电源电压的电阻器 - 电容器（RC）电路; 包括用于在ESD事件期间保护IC的多个n型场效应晶体管（nFET）的ESD钳位; 触发电路，用于接收RC电路的输出并产生触发脉冲以在ESD事件期间导通ESD钳位; 以及连接到触发电路的nFET偏置选择电路，nFET偏置选择电路，用于选择触发电路的低电压电源或负偏置电压源，使得触发电路响应于触发电路产生触发脉冲 选择负偏压电源，在正常工作期间关闭ESD钳位。
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公开(公告)号：US20130293991A1
公开(公告)日：2013-11-07
申请号：US13464131
申请日：2012-05-04
申请人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
发明人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
CPC分类号： H02H9/046
摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.
摘要翻译： 本发明提供一种用于消除电流泄漏的静电放电（ESD）保护装置及相关方法。 在一个实施例中，ESD保护装置包括：用于接收电源电压的电阻器 - 电容器（RC）电路; 包括用于在ESD事件期间保护IC的多个n型场效应晶体管（nFET）的ESD钳位; 触发电路，用于接收RC电路的输出并产生触发脉冲以在ESD事件期间导通ESD钳位; 以及连接到触发电路的nFET偏置选择电路，nFET偏置选择电路，用于选择触发电路的低电压电源或负偏置电压源，使得触发电路响应于触发电路产生触发脉冲 选择负偏压电源，在正常工作期间关闭ESD钳位。
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公开(公告)号：US08839054B2
公开(公告)日：2014-09-16
申请号：US13445187
申请日：2012-04-12
申请人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
发明人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译： 提供了具有冗余性和使用方法的只读存储器（ROM）。 具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。 一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。 字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。 提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。 提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。
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公开(公告)号：US20130211749A1
公开(公告)日：2013-08-15
申请号：US13396775
申请日：2012-02-15
IPC分类号： G01R31/308 , G06F19/00
CPC分类号： G01R31/311
摘要： A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.
摘要翻译： 半导体器件结构嵌入半导体芯片内，通过运行多个已知电流通过器件来校准光子发射光度标度。 该方法包括将至少一个光子发射装置嵌入到具有至少一个功能装置的集成电路中。 控制电流被施加到至少一个光子发射装置。 捕获由至少一个光子发射装置产生的光子发射强度。 计算出至少一个光子发射装置的电流密度。 测试电流被施加到所述至少一个功能装置。 捕获由至少一个功能装置产生的光子发射强度。 基于与计算出的至少一个光子发射装置的电流密度的比较来估计至少一个功能装置的电流密度。
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公开(公告)号：US09052356B2
公开(公告)日：2015-06-09
申请号：US13396775
申请日：2012-02-15
IPC分类号： G01R31/00 , G01R31/311
CPC分类号： G01R31/311
摘要： A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.
摘要翻译： 半导体器件结构嵌入半导体芯片内，通过运行多个已知电流通过器件来校准光子发射光度标度。 该方法包括将至少一个光子发射装置嵌入到具有至少一个功能装置的集成电路中。 控制电流被施加到至少一个光子发射装置。 捕获由至少一个光子发射装置产生的光子发射强度。 计算出至少一个光子发射装置的电流密度。 测试电流被施加到所述至少一个功能装置。 捕获由至少一个功能装置产生的光子发射强度。 基于与计算出的至少一个光子发射装置的电流密度的比较来估计至少一个功能装置的电流密度。
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8.发明申请CONTENT ADDRESSABLE MEMORY WITH HIDDEN TABLE UPDATE, DESIGN STRUCTURE AND METHOD 审中-公开内容可寻址存储器，具有隐藏表更新，设计结构和方法公开(公告)号：US20090240875A1
公开(公告)日：2009-09-24
申请号：US12050340
申请日：2008-03-18
申请人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
发明人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
CPC分类号： G11C15/043 , G11C11/406
摘要： Disclosed are embodiments of memory circuit having two discrete memory devices with two discrete memory arrays that store essentially identical data banks. The first device is a conventional memory adapted to perform all maintenance operations that require read functions (i.e., all update and refresh operations). The second device is a DRAM-based CAM device adapted to perform parallel search and overwrite operations only. Performance of overwrite operations by the second device occurs in conjunction with performance of maintenance operations by the first device so that corresponding memory cells in the two devices store essentially identical data values. Since the data banks in the memory devices are essentially identical and since maintenance and parallel search operations are not performed by the same device, the parallel search operations can be performed without interruption. Also disclosed are embodiments of an associated design structure and method.
摘要翻译： 公开了具有两个分立存储器件的存储器电路的实施例，其具有存储基本上相同的数据库的两个分立存储器阵列。 第一设备是适于执行需要读取功能（即，所有更新和刷新操作）的所有维护操作的常规存储器。 第二设备是仅适用于执行并行搜索和重写操作的基于DRAM的CAM设备。 第二设备的覆盖操作的性能与第一设备的维护操作的性能一起发生，使得两个设备中的相应存储器单元存储基本上相同的数据值。 由于存储器件中的数据库基本上相同，并且由于维护和并行搜索操作不由同一设备执行，所以可以不中断地执行并行搜索操作。 还公开了相关设计结构和方法的实施例。
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公开(公告)号：US20110051484A1
公开(公告)日：2011-03-03
申请号：US12549494
申请日：2009-08-28
CPC分类号： G11C15/04 , G11C15/043
摘要： A dynamic, content addressable memory (CAM) cell includes a match line, a write line, a first pair of complementary bit lines for read and search operations, and a second pair of complementary bit lines for write operations; a first storage transistor connected between one of the first pair of complementary bit lines and the match line; a second storage transistor connected between the other of the first pair of complementary bit lines and the match line; a first write transistor connected between a gate of the first storage transistor and one of the second pair of complementary bit lines; and a second write transistor connected between a gate of the second storage transistor and the other of the second pair of complementary bit lines, with both the first and second write transistors having a gate connected to the write line.
摘要翻译： 动态内容可寻址存储器（CAM）单元包括匹配线，写入线，用于读取和搜索操作的第一对互补位线和用于写入操作的第二对互补位线; 连接在所述第一对互补位线之一与所述匹配线之间的第一存储晶体管; 连接在所述第一对互补位线中的另一对与所述匹配线之间的第二存储晶体管; 连接在所述第一存储晶体管的栅极和所述第二对互补位线之一中的第一写入晶体管; 以及连接在所述第二存储晶体管的栅极和所述第二对互补位线中的另一个之间的第二写入晶体管，所述第一和第二写入晶体管都具有连接到所述写入线的栅极。
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10.发明申请公开(公告)号：US20080169839A1
公开(公告)日：2008-07-17
申请号：US11851133
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/0175
CPC分类号： H03K19/0963
摘要： A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译： 一种用于集成电路的设计结构，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。 栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。
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