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公开(公告)号：US08519772B2
公开(公告)日：2013-08-27
申请号：US13075652
申请日：2011-03-30
IPC分类号： H03K17/687
CPC分类号： H03K19/0016
摘要： Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.
摘要翻译： 在集成电路中实现交流电源门控的结构和方法。 半导体结构包括电源门控电路，其包括一组电源门开关和产生使能信号的交替使能发生器。 每个相应的一个功率门开关由使能信号中的相应一个使能。 交替发电机产生使能信号，使得第一使能电源门极开关在一组电源门开关之间交替。
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公开(公告)号：US20120249213A1
公开(公告)日：2012-10-04
申请号：US13075652
申请日：2011-03-30
CPC分类号： H03K19/0016
摘要： Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.
摘要翻译： 在集成电路中实现交流电源门控的结构和方法。 半导体结构包括电源门控电路，其包括一组电源门开关和产生使能信号的交替使能发生器。 每个相应的一个功率门开关由使能信号中的相应一个使能。 交替发电机产生使能信号，使得第一使能电源门极开关在一组电源门开关之间交替。
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公开(公告)号：US09070791B2
公开(公告)日：2015-06-30
申请号：US11923864
申请日：2007-10-25
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译： 公开了作为电容器操作的设计结构晶体管的实施例以及在这种电容器内调谐电容的相关方法。 电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。 通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/漏极区域中的电压条件来选择性地在两个不同的值之间改变电容器所呈现的电容值。 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。 根据每个通道区域中的电导率，电容器将呈现不同的电容值。
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公开(公告)号：US07821053B2
公开(公告)日：2010-10-26
申请号：US11560126
申请日：2006-11-15
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译： 公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。 电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。 通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。 根据每个通道区域中的电导率，电容器将呈现不同的电容值。
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公开(公告)号：US07619398B2
公开(公告)日：2009-11-17
申请号：US12120255
申请日：2008-05-14
摘要： Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.
摘要翻译： 这里公开了一种用于控制片上配电网络的电源电压的系统。 该系统集成了可编程片上感测网络，可在多个位置选择性地连接到配电网络。 当感测网络在最佳感测点选择性地连接到配电网络时，产生来自该最佳感测点的局部电压反馈信号并用于调整电源电压，并且因此来管理整个配电网络的电压分布 网络。 此外，该系统包括用于管理配电网络上的电压分布的策略，用于对配电网络上的压降进行分析的装置以及用于基于策略和配置文件选择最佳感测点的装置。 该系统的另一实施例可以进一步控制同一芯片上的多个配电网络的电源电压。
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6.发明授权公开(公告)号：US07348657B2
公开(公告)日：2008-03-25
申请号：US11425491
申请日：2006-06-21
IPC分类号： H01L29/06
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.
摘要翻译： 一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。 半导体器件优选为二极管结型。
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公开(公告)号：US06493257B1
公开(公告)日：2002-12-10
申请号：US10108687
申请日：2002-03-27
IPC分类号： G11C11412
CPC分类号： G11C14/00
摘要： A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being saved in the first latch.
摘要翻译： 一种状态保存电路及其使用方法。 电路包括由不间断电源供电的第一锁存器，其中第一锁存器包括用于存储数据的第一对交叉耦合的反相器，并且包括用于隔离第一对交叉耦合的反相器中的数据的输入截止控制; 耦合到所述第一锁存器的输出并由可中断电源供电的第二锁存器，其中所述第二锁存器包括第二对交叉耦合的反相器和用于将所述数据从所述第一锁存器锁存到所述第二锁存器的时钟输入; 并且其中对所述第二锁存器的电力中断导致在所述第一锁存器中保存状态。
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公开(公告)号：US6087881A
公开(公告)日：2000-07-11
申请号：US121515
申请日：1998-07-23
申请人： Francis Chan , Jeffrey H. Sloan , Douglas W. Stout
发明人： Francis Chan , Jeffrey H. Sloan , Douglas W. Stout
IPC分类号： H03K19/003 , H03L5/00
CPC分类号： H03K19/00315
摘要： A dual stage voltage level predrive circuit for an integrated circuit chip including two level shifter stages in series. The voltage level shifting circuit uses single dielectric layer devices and three bias supply circuits each providing a different DC bias voltage for distributing bias voltages among the devices such that dielectric voltage stress across single dielectric layers is reduced. The first stage of the level shifting circuit receives a first input signal having a first voltage swing, converts the first voltage swing to a second voltage swing and provides a first output signal corresponding to the first input signal and having the second voltage swing. The second stage of the level shifting circuit receives the first output signal from the first stage, converts the second voltage swing to a third voltage swing and provides a final output signal having the third voltage swing.
摘要翻译： 一种用于集成电路芯片的双级电压电平预调制电路，包括两个电平转换级串联。 电压电平移位电路使用单个电介质层器件和三个偏置电源电路，每个偏置电源电路提供不同的直流偏置电压，用于在器件之间分配偏置电压，从而降低跨单个电介质层的介电电压应力。 电平移位电路的第一级接收具有第一电压摆幅的第一输入信号，将第一电压摆幅转换为第二电压摆幅，并提供对应于第一输入信号并具有第二电压摆幅的第一输出信号。 电平移位电路的第二级接收来自第一级的第一输出信号，将第二电压摆幅转换为第三电压摆幅，并提供具有第三电压摆幅的最终输出信号。
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公开(公告)号：US20080224733A1
公开(公告)日：2008-09-18
申请号：US11684890
申请日：2007-03-12
CPC分类号： H03K19/09429
摘要： The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode.
摘要翻译： 这里的发明涉及用于与I / O电路一起使用的本发明的总线保持器和逻辑电路，例如用于I / O缓冲器电路的接收器侧。 本发明的电路将IC功能的一条数据线连接到三态总线的一条线路（每总线或线路的一位数据）。 母线保护器和逻辑控制电路与I / O功能驱动器保持隔离，并且响应于通常由IC或SOC提供的三态信号（TS）或正常I / O接收器中的I / O电路 侧面操作。 本发明的总线保持器和逻辑电路在存在三态使能信号的情况下，有选择地使驱动器输出焊盘处于三状态，上拉状态，下拉状态和总线保持模式状态，并且是 当I / O总线驱动缓冲电路处于驱动模式时禁用。
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公开(公告)号：US07142991B2
公开(公告)日：2006-11-28
申请号：US11095327
申请日：2005-03-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of, and a system for, determining an extreme value of a voltage dependent parameter of an integrated circuit design is provided. The method includes determining a plurality of current waveforms, each of the plurality of waveforms corresponding to one of a plurality of aggressor objects in the design of the integrated circuit; applying each of the plurality of current waveforms to a subset of the plurality of power bus nodes, the subset of the plurality of power bus nodes being designed to supply power to a corresponding one of the plurality of aggressor objects; determining a plurality of voltage waveforms, each of the plurality of voltage waveforms being at one of the plurality of power bus nodes and corresponding to one of the plurality of current waveforms; using the plurality of voltage waveforms to determine the extreme value.
摘要翻译： 提供了一种用于确定集成电路设计的电压相关参数的极值的方法和系统。 所述方法包括确定多个电流波形，所述多个波形中的每一个对应于所述集成电路的设计中的多个侵略对象中的一个; 将所述多个电流波形中的每一个应用于所述多个电力总线节点的子集，所述多个电力总线节点的子集被设计为向所述多个侵权者对象中的相应一个提供电力; 确定多个电压波形，所述多个电压波形中的每一个在所述多个电力总线节点中的一个处并且对应于所述多个电流波形中的一个; 使用多个电压波形来确定极值。
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