摘要:
A novel method and apparatus is disclosed, that embeds with, or otherwise makes available to an adaptive equalizer, suitable for use in IEEE 1OG-LRM standard compliant receivers, digital logic that monitors some of the Layer 1 and preferably some of the Layer 2 processing that typically occurs after the equalization step during decoding and processing of the record data stream. From this additional logic information, the equalizer is able to make a much more accurate prediction of equalizer convergence by counting processing errors and prove convergence by calculation of BER. The novel method and apparatus are applicable to ASIC embodiments and the complexity of the logic information obtained can be programmably scaled back or enhanced as appropriate in light of the particular communication environment.
摘要:
A novel method and apparatus is disclosed, that embeds with, or otherwise makes available to an adaptive equalizer, suitable for use in IEEE 10G-LRM standard compliant receivers, digital logic that monitors some of the Layer 1 and preferably some of the Layer 2 processing that typically occurs after the equalization step during decoding and processing of the record data stream. From this additional logic information, the equalizer is able to make a much more accurate prediction of equalizer convergence by counting processing errors and prove convergence by calculation of BER. The novel method and apparatus are applicable to ASIC embodiments and the complexity of the logic information obtained can be programmably scaled back or enhanced as appropriate in light of the particular communication environment.
摘要:
According to a first aspect, there is provided a circuit for recovering data received over a communication channel. The circuit includes an adaptive equalizer operable to remove ISI (intersymbol interference) from a received signal and a timing recovery circuit operable to sample recovered data. The timing recovery circuit includes a detector based on a Hogge Phase detector. According to another aspect, there is provided a module in which the circuit may be implemented. According to another aspect, there is provided a method for recovering data received over a communication channel. The method involves removing ISI from a received signal using an adaptive equalizer, and sampling recovered data using a detector based on a Hogge phase detector. According to another aspect, the timing recovery circuit includes a plurality of phase detectors, each one being operable to sample recovered data. A selector is provided for selecting which sampled recovered data is to be output.
摘要:
The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要:
According to a first aspect, there is provided a circuit for recovering data received over a communication channel. The circuit includes an adaptive equalizer operable to remove ISI (intersymbol interference) from a received signal and a timing recovery circuit operable to sample recovered data. The timing recovery circuit includes a detector based on a Hogge Phase detector. According to another aspect, there is provided a module in which the circuit may be implemented. According to another aspect, there is provided a method for recovering data received over a communication channel. The method involves removing ISI from a received signal using an adaptive equalizer, and sampling recovered data using a detector based on a Hogge phase detector. According to another aspect, the timing recovery circuit includes a plurality of phase detectors, each one being operable to sample recovered data. A selector is provided for selecting which sampled recovered data is to be output.
摘要:
The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要:
Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.
摘要:
An eye opener circuit is provided which performs a data re-timing/eye opening function on a data signal after having been corrupted by jitter. The circuit uses a PLL driven by a clock source which was the same clock source used in timing the data signal originally. The PLL generates a local clock used to re-time the data. A phase error may be introduced into the PLL, or into the data signal.
摘要:
Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.
摘要:
A first parameter correlated with a degree of a variation in the output from the air-fuel ratio sensor is calculated. A possible range of a second parameter representing a degree of a variation in air-fuel ratio among the cylinders is determined based on the first parameter. The first parameter is calculated with an air-fuel ratio of a predetermined cylinder forcibly changed. A difference between the unchanged first parameter and the forcibly changed first parameter is determined. A first characteristic representing a relation between the second parameter and the difference is determined based on the possible range of the second parameter and the difference. One of the determination value and the first parameter calculated before the forced change is corrected based on inclination of the determined first characteristic.