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公开(公告)号：US5642139A
公开(公告)日：1997-06-24
申请号：US235761
申请日：1994-04-29
CPC分类号： H04N21/4143 , G09G5/395 , G09G5/42 , H04N19/00 , H04N19/98
摘要： Motion video may be imported into a personal or portable computer through an I/O port having a limited data bandwidth, such as a PCMCIA interface. Motion video data is compressed by sub-sampling both luminance and chrominance difference data for different sized groups of pixels. The compression apparatus may be formed on a PCMCIA card which interfaces with a personal or portable computer. Motion video data, compressed by as much as 5:1 or 6:1, is transferred through the PCMCIA card to a host computer. The host computer may serialize the compressed data and store the data in serialized compressed format in a video memory of a video controller. The video controller is provided with decompression circuitry to decompress the motion video data into luminance and chrominance difference data. The luminance and chrominance difference data is converted into RGB data and displayed in a video display.
摘要翻译： 运动视频可以通过具有有限数据带宽的I / O端口（例如PCMCIA接口）导入个人或便携式计算机。 运动视频数据通过对不同大小的像素组的亮度和色差差分数据进行二次采样而被压缩。 压缩装置可以形成在与个人或便携式计算机接口的PCMCIA卡上。 压缩多达5：1或6：1的运动视频数据通过PCMCIA卡传输到主机。 主机可以串行化压缩数据，并将数据以串行压缩格式存储在视频控制器的视频存储器中。 视频控制器设置有解压缩电路，以将运动视频数据解压缩为亮度和色差差数据。 亮度和色差差数据被转换成RGB数据并显示在视频显示器中。
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公开(公告)号：US6023266A
公开(公告)日：2000-02-08
申请号：US764876
申请日：1996-12-03
CPC分类号： H04N21/4143 , G09G5/395 , G09G5/42 , H04N19/00 , H04N19/98
摘要： Motion video may be imported into a personal or portable computer through an I/O port having a limited data bandwidth, such as a PCMCIA interface. Motion video data is compressed by sub-sampling both luminance and chrominance difference data for different sized groups of pixels. The compression apparatus may be formed on a PCMCIA card which interfaces with a personal or portable computer. Motion video data, compressed by as much as 5:1 or 6:1, is transferred through the PCMCIA card to a host computer. The host computer may serialize the compressed data and store the data in serialized compressed format in a video memory of a video controller. The video controller is provided with decompression circuitry to decompress the motion video data into luminance and chrominance difference data. The luminance and chrominance difference data is converted into RGB data and displayed in a video display.
摘要翻译： 运动视频可以通过具有有限数据带宽的I / O端口（例如PCMCIA接口）导入个人或便携式计算机。 运动视频数据通过对不同大小的像素组的亮度和色差差分数据进行二次采样而被压缩。 压缩装置可以形成在与个人或便携式计算机接口的PCMCIA卡上。 压缩多达5：1或6：1的运动视频数据通过PCMCIA卡传输到主机。 主机可以串行化压缩数据，并将数据以串行压缩格式存储在视频控制器的视频存储器中。 视频控制器设置有解压缩电路，以将运动视频数据解压缩为亮度和色差差数据。 亮度和色差差数据被转换成RGB数据并显示在视频显示器中。
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3.发明授权
公开(公告)号：US5670973A
公开(公告)日：1997-09-23
申请号：US743413
申请日：1996-11-01
CPC分类号： G09G3/2011 , G09G3/3644 , G09G3/3681 , G09G3/3685 , G09G3/3692 , G09G3/3696 , G09G2320/0204 , G09G2320/0209 , G09G2320/041
摘要： A method and apparatus for compensating crosstalk in liquid crystal displays is disclosed which involves applying boost voltages to the rows and columns of the display in proportion to the number of ON pixels in a row or column, the number of transition between "ON-and-OFF" or "OFF-and-ON" in each column, and the position of the pixel in a row. "Boost" voltages are applied to each row as it is being actively scanned to provide horizontal crosstalk compensation, while "boost" voltages are applied to each column during the vertical retrace interval of the display sequence to provide vertical crosstalk compensation. In a preferred embodiment, the vertical crosstalk compensation is determined during the vertical retrace interval over several flames.
摘要翻译： 公开了一种用于补偿液晶显示器中的串扰的方法和装置，其涉及将显示器的行和列的升压电压与行或列中的ON像素的数量成正比，“ON- OFF“或”OFF-ON“，以及像素在一行中的位置。 “Boost”电压被施加到每一行，因为它被主动地扫描以提供水平串扰补偿，而在显示序列的垂直回扫间隔期间，“升压”电压被施加到每列，以提供垂直串扰补偿。 在优选实施例中，在几个火焰的垂直回扫间隔期间确定垂直串扰补偿。
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公开(公告)号：US5608864A
公开(公告)日：1997-03-04
申请号：US235764
申请日：1994-04-29
申请人： Rakesh K. Bindlish , Vlad Bril , Alexander Eglit
发明人： Rakesh K. Bindlish , Vlad Bril , Alexander Eglit
IPC分类号： G06F3/14 , G06F3/048 , G06F3/153 , G09G5/00 , G09G5/14 , G09G5/36 , G09G5/38 , H04N5/265 , H04N5/45 , G06F12/00
CPC分类号： G09G5/14 , H04N5/45 , G09G2340/125
摘要： A computer video controller, particularly a VGA or SVGA video controller for use with graphical user interface (GUI) software such as WINDOWS.TM. or OS/2.TM. is provided with two video data pipelines for simultaneously displaying full motion video within a window in a video display. A first data pipeline displays background video at a first pixel depth. A second data pipeline is provided to display a motion video window at a second, usually higher, pixel depth. The location of the motion video window is measured horizontally in number of memory fetch cycles needed to retrieve the horizontal scan line of pixel data abutting the motion video window. The width of the motion video window is measured in the number of memory fetches required to retrieve one scan line of the motion video window. By providing two parallel data pipelines having equal delays, the motion video window can be generated by selectively retrieving background pixel data or motion video window pixel data and transferring the data to the appropriate pipeline. In an alternative embodiment, data tags may be used to distinguished between background and motion video window pixel data. The controller may also support various compression formats for motion video.
摘要翻译： 具有用于诸如WINDOWS TM或OS / 2 TM的图形用户界面（GUI）软件的VGA或SVGA视频控制器的计算机视频控制器被提供有两个视频数据流水线，用于在视频窗口中同时显示全部运动视频 显示。 第一数据流水线以第一像素深度显示背景视频。 提供第二数据流水线以在第二通常较高的像素深度处显示运动视频窗口。 水平地测量运动视频窗口的位置以检索与运动视频窗口相邻的像素数据的水平扫描行所需的存储器提取周期数。 以检索运动视频窗口的一条扫描线所需的存储器提取量来测量运动视频窗口的宽度。 通过提供具有相等延迟的两个并行数据流水线，可以通过选择性地检索背景像素数据或运动视频窗口像素数据并将数据传送到适当的流水线来生成运动视频窗口。 在替代实施例中，可以使用数据标签来区分背景和运动视频窗口像素数据。 控制器还可以支持用于运动视频的各种压缩格式。
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公开(公告)号：US5611041A
公开(公告)日：1997-03-11
申请号：US359315
申请日：1994-12-19
申请人： Vlad Bril , Alexander Eglit , Sagar W. Kenkare
发明人： Vlad Bril , Alexander Eglit , Sagar W. Kenkare
IPC分类号： G06F12/00 , G06F12/02 , G09G5/00 , G09G5/14 , G09G5/18 , G09G5/36 , G09G5/39 , G09G5/393 , G09G5/395 , G09G5/40
摘要： A memory controller, particularly for use in a video controller, is provided which reduces the effect of page misses during memory access. A video port FIFO is provided for buffering data from a video port to a display memory. A CRT FIFO is provided for buffering data from a display memory to a display. If, during a video port FIFO cycle, a page miss is encountered, the video port FIFO cycle is terminated and processing passes to a CRT FIFO CYCLE. If a page miss is encountered during a CRT FIFO cycle, the subsequent video port FIFO cycle will shortened by a number of memory cycles to compensate for the additional memory cycles required by the page miss. Additional data accumulated in the video port FIFO may be transferred to the display memory during a retrace interval. In this manner, memory bandwidth is optimized by removing a non-aligned page miss as the worst case of memory bandwidth utilization.
摘要翻译： 提供了特别用于视频控制器的存储器控制器，其减少了存储器访问期间页错误的影响。 视频端口FIFO被提供用于缓冲从视频端口到显示存储器的数据。 提供CRT FIFO用于将数据从显示存储器缓存到显示器。 如果在视频端口FIFO周期期间遇到页面未命中，则视频端口FIFO周期终止，并且处理转到CRT FIFO CYCLE。 如果在CRT FIFO周期期间遇到页错，则后续视频端口FIFO周期将缩短多个存储周期，以补偿页错过所需的额外存储周期。 视频端口FIFO中积累的附加数据可以在回扫间隔期间传送到显示存储器。 以这种方式，通过消除不对齐的页面遗漏作为存储器带宽利用的最坏情况来优化存储器带宽。
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6.发明授权Method and apparatus for providing LCD panel protection in an LCD display controller 失效在LCD显示控制器中提供LCD面板保护的方法和装置公开(公告)号：US06310599B1
公开(公告)日：2001-10-30
申请号：US08704842
申请日：1996-08-28
IPC分类号： G09G333
CPC分类号： G09G3/36 , G09G2330/02 , G09G2330/04
摘要： A flat panel display controller is provided with a circuit for monitoring clocking signal(s) to the flat panel display. A clocking signal output to the flat panel display may be fed back to the display controller using a conventional I/O pad. In the preferred embodiment, the fed back clocking signal resets a counter. In a second embodiment, the fed back clocking signal may then pass through an edge detector whose output then resets the counter. The counter will overflow if a edge signal is not received within a predetermined time period. If an overflow occurs, the carry signal of the counter will initiate a flat panel power shutdown through power control circuitry. The clock signal for the counter may be derived from an off-chip oscillator such that if a failure occurs within the display controller, the counter will continue to function.
摘要翻译： 平板显示控制器设置有用于监视平板显示器的时钟信号的电路。 输出到平板显示器的定时信号可以使用传统的I / O垫反馈到显示控制器。 在优选实施例中，反馈时钟信号复位计数器。 在第二实施例中，反馈时钟信号然后可以通过边沿检测器，其输出然后复位该计数器。 如果在预定时间段内没有接收到边缘信号，计数器将溢出。 如果发生溢出，计数器的进位信号将通过电源控制电路启动平板电源关闭。 计数器的时钟信号可以从片外振荡器导出，使得如果在显示控制器内发生故障，则计数器将继续工作。
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7.发明授权Flicker filter and interlacer implemented in a television system displaying network application data 失效在显示网络应用数据的电视系统中实现的闪烁滤波器和交错器
公开(公告)号：US6072530A
公开(公告)日：2000-06-06
申请号：US1304
申请日：1997-12-31
申请人： Vlad Bril
发明人： Vlad Bril
CPC分类号： H04N7/012 , H04N7/0132 , Y10S348/91
摘要： A television system (TV) with an interlaced display screen for displaying network application data. A flicker filter is preferably implemented as an infinite impulse response (IIR) filter to eliminate sharp transitions in the network application data images. A random access memory is used to store the lines of the filtered images and any adjacent lines used for the filtering operation. Alternate lines of the filtered images are retrieved from the random access memory to provide an interlaced image of the filtered network application data images. The interlaced images are displayed on an interlaced display unit of a television system.
摘要翻译： 一种具有用于显示网络应用数据的隔行显示屏幕的电视系统（TV）。 闪烁滤波器优选地被实现为无限脉冲响应（IIR）滤波器，以消除网络应用数据图像中的尖锐转变。 随机存取存储器用于存储过滤图像的行和用于过滤操作的任何相邻行。 从随机存取存储器检索滤波图像的替代行，以提供经过滤网络应用数据图像的隔行扫描图像。 隔行扫描图像显示在电视系统的隔行显示单元上。
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公开(公告)号：US6067071A
公开(公告)日：2000-05-23
申请号：US673793
申请日：1996-06-27
CPC分类号： G09G5/005 , G09G2340/0407 , G09G5/006 , G09G5/18
摘要： A display controller in a computer system controls the output of graphics display data in a computer system having a fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a Discrete Time Oscillator (DTO) based clock divider and DCT based polyphase interpolation to upscale graphics display data from a first resolution to the panel resolution. DTO clock divider circuit synchronizes scan clocks between the input resolution and the desired output resolution. Within graphics display area, MVA.TM. display at greater color depth and resolution may be accommodated by additional DTO divider and interpolation steps.
摘要翻译： 计算机系统中的显示控制器控制具有固定分辨率平板显示器的计算机系统中的图形显示数据的输出。 固定面板显示器可能会显示非本地分辨率，特别是在较低分辨率下。 本发明的控制器使用基于离散时间振荡器（DTO）的时钟分频器和基于DCT的多相插值来将图形显示数据从第一分辨率升高到面板分辨率。 DTO时钟分频器电路在输入分辨率和所需输出分辨率之间同步扫描时钟。 在图形显示区域内，可以通过附加的DTO分频器和插值步骤来适应更大颜色深度和分辨率的MVA TM显示。
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公开(公告)号：US6118413A
公开(公告)日：2000-09-12
申请号：US136791
申请日：1998-08-19
申请人： Vlad Bril , Rakesh Bindlish , Ken Fuiks , Robin Sungsoo Han , Sridhar Kotha , Alexander Julian Eglit
发明人： Vlad Bril , Rakesh Bindlish , Ken Fuiks , Robin Sungsoo Han , Sridhar Kotha , Alexander Julian Eglit
CPC分类号： G06F3/1431 , G09G2360/04 , G09G3/2051 , G09G5/39 , G09G5/395
摘要： A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g., LCD and CRT) are provided to temporarily store video data. FIFO pointers are fed back to a sequence controller to drive data read cycles from display memory. The use of tags and FIFO pointer feedback allows two video displays to be driven at different data rates, allowing for independent resolution and refresh rates in each display.
摘要翻译： 一种用于控制具有独立的刷新率和像素分辨率的至少两个视频显示器的视频控制器。 在第一实施例中，在每个视频显示器（例如CRT和LCD）的视频控制器内提供两个单独的数据路径。 利用64位宽的DRAMS的带宽增加，可以在单独的读取周期中检索每个数据路径的数据。 每个数据通路可以在其自己的时钟频率下操作刷新率和像素分辨率的特性。 双数据路径实施例还降低了驱动这种双显示器所需的软件模型的复杂性。 在替代实施例中，可以在视频控制器内提供单个数据路径来驱动具有独立刷新率和像素分辨率的两个视频显示器的数据。 附加到通过指示视频数据的目的地（例如，CRT或LCD）的数据路径的每个字或双字的数据“标签”（额外位）。 在数据路径的输出端，提供分离的FIFO（例如LCD和CRT）以临时存储视频数据。 FIFO指针被反馈到序列控制器以从显示存储器驱动数据读取周期。 使用标签和FIFO指针反馈允许以不同的数据速率驱动两个视频显示器，允许在每个显示器中独立分辨率和刷新率。
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10.发明授权Method and apparatus for enabling a user to access data network applications from a television system 有权用于使用户能够从电视系统接入数据网络应用的方法和装置
公开(公告)号：US6057888A
公开(公告)日：2000-05-02
申请号：US301443
申请日：1999-04-28
申请人： Vlad Bril
发明人： Vlad Bril
IPC分类号： G06F3/14 , G09G5/14 , H04N5/445 , H04N9/64 , H04N21/462
CPC分类号： G06F3/14 , H04N21/4312 , H04N21/4435 , H04N21/478 , H04N5/44504 , H04N5/44591 , G09G2340/125 , G09G5/14 , H04N21/4622 , H04N5/445 , H04N9/641
摘要： A television system (TV) which enables a user to view display represented by a television signal as well as to access data network applications. The TV includes an on-screen-display (OSD) controller which stores the network application data and other display entities in a memory module as separate bit maps. A single image for display on a TV display screen is generated by overlaying all the display entities (including television signal, network application data, pointer, and low resolution data) according to a predetermined priority. Display entities (other than TV signal) are stored in separate portions of the memory module as independent surfaces to enable the displays of individual display entities to be generated and modified according to the individual display entity requirements.
摘要翻译： 一种使用户能够观看由电视信号表示的显示以及访问数据网络应用的电视系统（TV）。 电视机包括屏幕显示（OSD）控制器，其将网络应用程序数据和其他显示实体存储在存储器模块中作为单独的位图。 通过根据预定的优先级覆盖所有显示实体（包括电视信号，网络应用数据，指针和低分辨率数据）来生成用于在TV显示屏幕上显示的单个图像。 显示实体（电视信号除外）作为独立表面存储在存储器模块的分开的部分中，以使得可以根据各个显示实体要求来生成和修改各个显示实体的显示。
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