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    Apparatus for adjusting the timing of sampled data signals in a resampling system
    8.
    发明授权
    Apparatus for adjusting the timing of sampled data signals in a resampling system 失效
    用于在重采样系统中调整采样数据信号的定时的装置

    公开(公告)号：US5268750A

    公开(公告)日：1993-12-07

    申请号：US861251

    申请日：1992-03-31

    申请人： Kevin J. Stec ,  Kenneth E. Vavreck ,  Jerome D. Shields

    发明人： Kevin J. Stec ,  Kenneth E. Vavreck ,  Jerome D. Shields

    IPC分类号： H04N11/04 ,  H04N9/44 ,  H04N9/64 ,  H04N11/20

    CPC分类号： H04N9/44 ,  H04N11/20 ,  H04N9/64

    摘要： A video signal processing system uses a sequence of interpolation filters to resample a 125M video signal to produce a 244M signal. In addition, the system allows an operator to specify a desired subcarrier-to-horizontal sync (SCH) phase and a desired horizontal position. The system automatically adjusts the starting point in the sequence of filters used for the resampling operation to implement each of the requested phase shifts.

    摘要翻译： 视频信号处理系统使用内插滤波器序列来重新采样125M视频信号以产生244M信号。 另外，该系统允许操作者指定期望的子载波到水平同步（SCH）相位和期望的水平位置。 系统自动调整用于重采样操作的滤波器序列中的起始点，以实现每个所请求的相移。

    Phase locked loop synchronizer for a resampling system having incompatible input and output sample rates
    9.
    发明授权
    Phase locked loop synchronizer for a resampling system having incompatible input and output sample rates 失效
    用于具有不兼容输入和输出采样率的重采样系统的锁相环同步器

    公开(公告)号：US5335074A

    公开(公告)日：1994-08-02

    申请号：US96635

    申请日：1993-07-23

    申请人： Kevin J. Stec

    发明人： Kevin J. Stec

    IPC分类号： H04L7/033 ,  H04N5/12 ,  H04N5/44 ,  H04N7/01 ,  H04N9/64 ,  H04N11/16 ,  H04N11/20 ,  H04N5/04 ,  H04N5/06

    CPC分类号： H04N11/16 ,  H04N11/20 ,  H04N5/44 ,  H04N9/64

    摘要： A video signal conversion system converts input video signals in a studio format, such as CCIR 601 (625/25), into output video signals in another format, such as the Phase Alternate Line (PAL) format. The horizontal line scanning frequency of the input and output signals is the same. The signal conversion system uses an output clock signal to determine the relative timing of the input and output video signals. This signal is generated by a phase-locked loop which employs a crystal-controlled VCO. The phase of the signal produced by the VCO is adjusted to maintain the sampling clock signals of the input and output video signals in a predetermined phase relationship. The phase error signal which is used to control the VCO is generated by comparing a first phase reference signal, generated from the output signal, to a second phase reference signal generated from the input signal. The output phase reference signal may be the synchronizing signal component of the converted video signal or an indication that a predetermined interpolation phase is being applied by the resampling system. The input phase reference signal may be the input clock signal or an indication of the start of a horizontal line interval.

    摘要翻译： 视频信号转换系统将诸如CCIR 601（625/25）的演播室格式的输入视频信号转换为诸如相位交替行（PAL）格式的另一种格式的输出视频信号。 输入和输出信号的水平线扫描频率相同。 信号转换系统使用输出时钟信号来确定输入和输出视频信号的相对定时。 该信号由采用晶体控制VCO的锁相环产生。 调整由VCO产生的信号的相位以将输入和输出视频信号的采样时钟信号保持在预定的相位关系。 用于控制VCO的相位误差信号通过将从输出信号产生的第一相位参考信号与从输入信号产生的第二相位参考信号进行比较而产生。 输出相位参考信号可以是经转换的视频信号的同步信号分量或由重采样系统施加预定内插相位的指示。 输入相位参考信号可以是输入时钟信号或水平行间隔开始的指示。

    Generation of synchronization samples for a digital PAL signal
    10.
    发明授权
    Generation of synchronization samples for a digital PAL signal 失效
    生成数字PAL信号的同步采样

    公开(公告)号：US5268756A

    公开(公告)日：1993-12-07

    申请号：US859843

    申请日：1992-03-30

    申请人： Kenneth E. Vavreck ,  Kevin J. Stec

    发明人： Kenneth E. Vavreck ,  Kevin J. Stec

    IPC分类号： H04N7/01 ,  H04N7/56 ,  H04N9/64 ,  H04N11/16

    CPC分类号： H04N9/642 ,  H04N11/162 ,  H04N7/0125 ,  H04N7/56

    摘要： A system for converting a digital component video signal having timing information contained therein to a digital composite video signal is described. The system has a decoder for extracting the timing information from the digital component signal, a digital memory means for storing portions of the desired digital composite signal, a memory control means for extracting the portions of said desired signal from the digital memory means in response to the timing information and a multiplexing means for combining the portions of the signal extracted from the digital memory in response to timing information of the digital component signal.